Analog Devices Inc. ADP3110KRZ

Overview

ADP3110KRZ from onsemi is a dual high-voltage N-channel MOSFET driver optimized for synchronous buck converters, featuring bootstrapped high-side drive, anticross-conduction protection, and output disable (OD) control per Intel® VRM 10 specification. It delivers 3.8 Ω high-side sourcing resistance, 1.4 Ω low-side sinking resistance, and 25 ns propagation delay driving 3 nF loads - enabling efficient multiphase CPU power delivery up to 500 kHz.

For engineers reviewing the ADP3110KRZ datasheet, ADP3110KRZ pinout, ADP3110KRZ application, or ADP3110KRZ equivalent, key selection criteria include its SOIC_N-8 package, 0°C to 85°C operating range, 4.15 V to 13.2 V VCC supply, OD-controlled floating output state, and integrated overlap protection preventing shoot-through in buck topologies.

Technical Context

The ADP3110KRZ implements adaptive overlap protection by monitoring the SW node voltage to enforce turn-off of the high-side MOSFET before enabling the low-side, with a fixed 150 ns delay if SW fails to rise first. Its high-side driver uses external bootstrap circuitry (BST–SW) to sustain gate drive during floating operation, while the low-side driver operates referenced to PGND.

Control logic accepts a single PWM input (IN) to generate complementary, nonoverlapping DRVH and DRVL outputs - DRVH in phase with IN, DRVL inverted - with built-in hysteresis (90–250 mV) on both IN and OD inputs for noise immunity. The OD pin forces both outputs low to float the output stage during system shutdown.

Key Specifications

Pinout & Package

ADP3110KRZ is housed in an 8-lead SOIC_N (R-8) package per JEDEC MS-012-AA, with 1.27 mm pitch, 4.9 mm × 3.9 mm body, and 1.75 mm max height. Thermal resistance is 123°C/W (2-layer board) or 90°C/W (4-layer board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET driver applications.

Compared with IR2110PbF and LM5113MMX/NOPB, ADP3110KRZ uniquely integrates VRM 10–compliant OD control, adaptive SW-based overlap protection, and matched high-/low-side timing - making it purpose-built for desktop/server CPU power stages rather than general-purpose or high-voltage bridges.

Availability

ADP3110KRZ is available at Aetrix Electronics and suitable for desktop CPU voltage regulators, multiphase VRM modules, and single-supply synchronous buck converters requiring stable component supply, long-term lifecycle support, and traceable Pb-free sourcing.

Supply support for ADP3110KRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, high-performance silicon solutions for automotive, industrial, cloud computing, and consumer electronics markets.

The ADP3110KRZ belongs to onsemi's high-performance power management IC portfolio, specifically engineered for precision synchronous buck gate driving in Intel VRM-compliant CPU power delivery systems.

FAQ

What is the maximum allowable BST-to-SW voltage for ADP3110KRZ?

The absolute maximum BST-to-SW voltage for ADP3110KRZ is +15 V, as specified in the Absolute Maximum Ratings table. Exceeding this limit risks permanent damage to the high-side driver output stage. In normal operation, BST is typically biased 12 V above SW using a bootstrap capacitor; design must ensure transient spikes remain within the 15 V ceiling, especially during fast dV/dt events at the switch node.

Does ADP3110KRZ require external bootstrap components, and what are the critical values?

Yes, ADP3110KRZ requires external bootstrap components: a diode (D1), primary bootstrap capacitor (C_BST1), secondary capacitor (C_BST2), and series resistor (R_BST). Per the datasheet, C_BST1 must withstand ≥50 V and be sized using Q_GATE and V_CC; for a 12 V system with 12 nC gate charge, C_BST1 = 12 nF. R_BST should be 1.5 Ω to 2.2 Ω to limit peak current and damp ringing, rated for ≥250 mW.

How does the overlap protection circuit in ADP3110KRZ prevent shoot-through?

The ADP3110KRZ overlap protection monitors the SW pin voltage after the high-side MOSFET turns off. It delays low-side turn-on until SW falls to ≤1 V - confirming high-side is fully off - or applies a fixed 150 ns delay if SW fails to rise first. This adaptive timing, independent of temperature, supply, or MOSFET parameters, guarantees nonoverlap and eliminates shoot-through current in the external power stage.

Can ADP3110KRZ drive both high-side and low-side MOSFETs with a single PWM input?

Yes, ADP3110KRZ accepts a single PWM input (IN) and internally generates complementary, nonoverlapping DRVH and DRVL outputs: DRVH is in phase with IN, while DRVL is inverted. No external logic or delay circuits are needed - the device handles phase relationship, dead-time insertion, and overlap prevention autonomously, simplifying PCB layout and reducing BOM count.

What is the purpose of the OD pin on ADP3110KRZ, and how is it used in VRM 10 systems?

The OD (Output Disable) pin on ADP3110KRZ is an active-low control that forces both DRVH and DRVL outputs low, disconnecting the gate drives and allowing the output to float. In VRM 10 systems, OD is asserted during processor shutdown to prevent uncontrolled discharge of bulk output capacitors through the synchronous rectifier, ensuring controlled power-down per Intel specification.