Analog Devices Inc. ADP3120AJRZ

Overview

ADP3120AJRZ from Analog Devices is a dual high-voltage N-channel MOSFET driver optimized for synchronous buck converters, featuring bootstrapped high-side drive, anticross-conduction protection, output disable (OD) functionality, and 45 ns propagation delay into 3 nF load. It operates across 0°C to 85°C and supports CPU VR applications with Flex-Mode™ controller compatibility.

For engineers reviewing the ADP3120AJRZ datasheet, ADP3120AJRZ pinout, ADP3120AJRZ application, or ADP3120AJRZ equivalent, key selection criteria include bootstrap-enabled high-side drive capability, overlapping protection timing, OD-controlled shutdown behavior, thermal performance in SOIC_N package, and verified compatibility with Intel VRD 10.x-compliant multiphase CPU supplies.

Technical Context

The ADP3120AJRZ integrates independent high-side and low-side drivers sharing one PWM input, with adaptive overlap protection that monitors SW node voltage to enforce dead-time-requiring SW to fall below 1 V before DRVL activation. Its BST-SW bootstrap architecture enables floating high-side gate drive up to 26 V, while internal logic ensures DRVH is in-phase and DRVL is 180° out-of-phase with IN.

It implements fixed 150 ns minimum delay when SW fails to reach VIN pre-turn-on, and includes UVLO (1.5–3.0 V) on VCC with 350 mV hysteresis. The OD pin forces both DRVH and DRVL low simultaneously, preventing rapid output capacitor discharge during system shutdown.

Key Specifications

Pinout & Package

ADP3120AJRZ is packaged in an 8-lead SOIC_N (R-8) with exposed pad not present; pinout matches JEDEC MS-012-AA standard. Pin assignments are validated per Analog Devices Rev. 0 datasheet Figure 2 and Table 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual synchronous buck driver applications.

Compared with IR2110SPbF and LM5113MMX/NOPB, ADP3120AJRZ offers hardware-enforced overlap timing tied to actual SW node behavior-reducing design risk in high-density CPU VRMs-while maintaining compact SOIC_N footprint and direct Flex-Mode™ controller interoperability.

Availability

ADP3120AJRZ is available at Aetrix Electronics and suitable for desktop CPU voltage regulators, server VRMs, and industrial embedded power supplies requiring stable component supply, long-lifecycle availability, and consistent parametric performance across production batches.

Supply support for ADP3120AJRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, power management, and signal conditioning.

The ADP3120AJRZ belongs to Analog Devices' power management driver product line, designed specifically for high-efficiency, multiphase synchronous buck converters in computing and communications infrastructure applications.

FAQ

What is the function of the SW pin on the ADP3120AJRZ?

The SW pin on the ADP3120AJRZ connects directly to the buck converter's switch node and serves two critical roles: it acts as the floating return reference for the high-side driver (DRVH), and it feeds the overlap protection circuit. This circuit monitors SW voltage to ensure the high-side MOSFET is fully off before enabling the low-side driver-preventing shoot-through under all operating conditions including temperature and load variation. The ADP3120AJRZ requires SW to fall below ~1 V before DRVL activation.

Does the ADP3120AJRZ support 5 V-only operation?

Yes, the ADP3120AJRZ supports 5 V-only operation: its VCC supply range is specified from 4.15 V to 13.2 V, and its digital inputs (IN, OD) accept 2.0 V logic-high threshold-fully compatible with standard 5 V CMOS/TTL signaling. The ADP3120AJRZ maintains full timing performance (e.g., 45 ns typical propagation delay) and output drive strength down to 4.15 V, making it suitable for 5 V input rails without level-shifting.

How does the OD pin affect both driver outputs in the ADP3120AJRZ?

The OD (Output Disable) pin on the ADP3120AJRZ is an active-low control that forces both DRVH and DRVL outputs low simultaneously, regardless of the state of the IN pin. This action halts switching in the external MOSFETs and prevents rapid discharge of the output capacitor during system shutdown or fault conditions. The ADP3120AJRZ specifies OD propagation delays of 20–55 ns (DRVH) and 20–190 ns (DRVL), ensuring deterministic, synchronized disable behavior critical for CPU power sequencing.

What bootstrap capacitor value is recommended for the ADP3120AJRZ?

Analog Devices recommends calculating the bootstrap capacitor (CBST1) using the formula C_BST1 = 10 × Q_GATE / (V_CC − V_D), where Q_GATE is the high-side MOSFET's total gate charge and V_D is the bootstrap diode forward drop. For example, with Q_GATE = 12 nC, V_CC = 12 V, and V_D = 1 V, CBST1 = 12 nF. The ADP3120AJRZ datasheet further specifies a minimum 50 V rating and recommends high-quality ceramic capacitors-verified in application circuits like Figure 16.

Is the ADP3120AJRZ pin-compatible with other members of the ADP3120 family?

Yes, the ADP3120AJRZ is pin-compatible with the ADP3120A series variants-including ADP3120AJCPZ (LFCSP_VD package)-as confirmed by identical pin numbering, functions, and electrical specifications in the Ordering Guide and Pin Configurations sections of the ADP3120A Rev. 0 datasheet. Both SOIC_N (JRZ) and LFCSP_VD (JCPZ) versions share identical BST, IN, OD, VCC, DRVH, SW, PGND, and DRVL pin assignments and timing behavior.