Analog Devices Inc. ADP3624ARHZ-RL
- Part No.:
- ADP3624ARHZ-RL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Gate Drivers
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Datasheet:
-
ADP3624ARHZ-RL.pdf
- Description:
- IC GATE DRVR LOW-SIDE 8MSOP
- Quantity:
- Payment:

- Shipping:

Inventory:14,615
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Product details
Overview
ADP3624ARHZ-RL from Analog Devices is a dual, noninverting 4 A low-side MOSFET driver in an 8-lead MINI_SO_EP package, operating from 4.5 V to 18 V supply, delivering 10 ns typical rise/fall times at 2.2 nF load, matched propagation delays (<2 ns), and integrated overtemperature warning/shutdown. It drives N-channel power MOSFETs in high-frequency synchronous rectification stages of DC-DC converters.
For engineers reviewing the ADP3624ARHZ-RL datasheet, ADP3624ARHZ-RL pinout, ADP3624ARHZ-RL application, or ADP3624ARHZ-RL equivalent, key selection criteria include input logic compatibility (3.3 V–capable), thermal protection thresholds (120°C warning / 150°C shutdown), parallel operation capability, SOIC_N_EP vs. MINI_SO_EP thermal resistance trade-offs (59°C/W vs. 43°C/W), and UVLO hysteresis (0.3 V) for stable startup under varying rail conditions.
Technical Context
The ADP3624ARHZ-RL implements dual independent noninverting gate drivers with internal pull-downs on INA/INB inputs, enabling safe default-off behavior when floating. Its SD pin features a precision comparator with 280 mV hysteresis and 1.28 V threshold, supporting redundant overvoltage protection schemes without external circuitry.
Thermal protection includes two discrete levels: open-drain OTW flag active low at 120°C–150°C (10°C hysteresis), and automatic shutdown at 150°C–180°C (30°C hysteresis). The device uses PGND-referenced output stage architecture optimized for ground-referenced N-MOSFETs, with 4 A peak source/sink current and <25 ns propagation delay variation across temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 4.5 V to 18 V - supports direct connection to common 5 V, 12 V, or 15 V bias rails without level shifting. |
| Rise/Fall Time | 10 ns typical @ 2.2 nF - enables >20 MHz switching in hard-switched topologies with minimal gate drive loss. |
| Peak Output Current | ±4 A - sufficient to charge/discharge high-QG MOSFETs (e.g., >100 nC) within sub-100 ns windows. |
| UVLO Hysteresis | 0.3 V - prevents oscillation during brown-out recovery and ensures clean power-up sequencing. |
| OTW Threshold | 120°C to 150°C - provides early thermal margin warning before critical junction temperature is reached. |
| Propagation Delay Match | <2 ns - maintains precise timing alignment between channels for interleaved or paralleled FET control. |
| Input Logic Compatibility | 3.3 V–compatible - interfaces directly with modern digital PWM controllers without external translators. |
Pinout & Package
ADP3624ARHZ-RL is housed in an 8-lead MINI_SO_EP package with exposed thermal pad (package option RH-8-1), offering 43°C/W θJA on JEDEC 4-layer board - optimized for compact, thermally demanding DC-DC modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SD) | Shutdown enable input | Active-high precision comparator input; pulls OUTA/OUTB low when asserted - used for system-level fault shutdown. |
| 2 (INA) | Noninverting channel A input | Direct logic-level interface; internal pull-down ensures OFF state if left unconnected. |
| 3 (PGND) | Power ground reference | Must be tied directly to MOSFET source node to minimize ground bounce and ensure accurate gate drive. |
| 4 (INB) | Noninverting channel B input | Independent from INA; supports asynchronous or synchronized dual-FET control. |
| 5 (OUTB) | Channel B gate drive output | Capable of ±4 A peak current; designed for low-inductance routing to MOSFET gate. |
| 6 (VDD) | Positive supply input | Requires local 4.7 µF MLCC + 100 nF ceramic bypass to PGND to suppress switching noise and sustain peak current. |
| 7 (OUTA) | Channel A gate drive output | Matched to OUTB in delay and drive strength - enables precise interleaving or paralleling. |
| 8 (OTW) | Overtemperature warning flag | Open-drain, active-low signal; wire-OR'able with other ADP362x devices for centralized thermal monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| Dual noninverting outputs | Enables direct drive of two independent low-side N-MOSFETs without external inverters or level shifters. |
| Parallel operation support | INA/INB and OUTA/OUTB can be tied together to double peak current drive and halve per-channel power dissipation. |
| Two-tier thermal protection | Separate OTW flag and hard shutdown provide both early warning and fail-safe die protection under overload or poor heatsinking. |
| Industry-standard pinout | Pin-compatible with legacy drivers (e.g., ADP3623/ADP3634 variants), simplifying drop-in upgrades in existing designs. |
| 3.3 V–compatible inputs | Accepts standard logic levels from microcontrollers, DSPs, or digital PWM ICs without external voltage translation. |
Applications
| AC-to-DC PFC Stage | Synchronous Buck Converter |
|---|---|
|
Use Scenario: Driving low-side switches in continuous conduction mode (CCM) boost PFC circuits operating at 65–100 kHz. IC Role / Device Role / Timing Role: Dual low-side gate driver providing matched, fast turn-on/turn-off of two parallel N-MOSFETs to minimize conduction losses and improve power factor. Use Value: 4 A peak current and 10 ns switching enable efficient handling of high gate charge MOSFETs (e.g., 120 nC), reducing switching losses by >15% versus lower-current drivers. |
Use Scenario: Controlling bottom FETs in multiphase buck regulators for CPU/GPU VRMs requiring tight phase alignment. IC Role / Device Role / Timing Role: Dual-channel driver delivering synchronized, low-jitter gate signals to paired low-side MOSFETs in each phase. Use Value: <2 ns inter-channel delay matching ensures phase current balance across multiple buck stages, improving transient response and thermal distribution. |
| Motor Drive Half-Bridge | Industrial DC-DC Module |
|
Use Scenario: Gate driving low-side N-MOSFETs in 24 V/48 V BLDC motor half-bridge inverters with regenerative braking. IC Role / Device Role / Timing Role: Robust low-side driver with integrated OTW flag feeding back to MCU for real-time thermal derating during stall or overload. Use Value: Open-drain OTW output allows direct connection to MCU GPIO with pull-up, eliminating need for external comparator or ADC monitoring. |
Use Scenario: Compact isolated DC-DC module (e.g., 48 V to 12 V) where PCB area and thermal performance are constrained. IC Role / Device Role / Timing Role: High-density gate driver in MINI_SO_EP package minimizing footprint while maintaining 43°C/W thermal resistance for reliable 300 kHz operation. Use Value: MINI_SO_EP package reduces board area by ~40% vs. SOIC_N_EP while lowering thermal resistance - critical for sealed or convection-cooled industrial modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual low-side MOSFET driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP3624ARDZ-RL | Same electrical specs and pinout, but in 8-lead SOIC_N_EP (RD-8-4) package with higher θJA = 59°C/W. | Better suited for prototyping or lower-power designs where thermal headroom exceeds 5 W; less space-constrained layouts. | Select ADP3624ARDZ-RL when board layout allows larger footprint and thermal management via copper pour is preferred over exposed-pad soldering. |
| LM5113SDX/NOPB | 4 A dual driver with 12 ns rise time, but only single overtemperature warning (no shutdown), 5 V–14 V supply range, and no SD hysteresis. | Lacks dual-tier thermal protection and precise SD comparator - requires external circuitry for redundant OVP/OCP. | Choose LM5113SDX/NOPB only when cost sensitivity outweighs need for integrated thermal safety and robust shutdown functionality. |
Compared with ADP3624ARHZ-RL, ADP3624ARDZ-RL trades thermal efficiency for ease of hand-soldering and test fixture compatibility, while LM5113SDX/NOPB offers lower unit cost but shifts thermal and fault-protection design burden to the system level - making ADP3624ARHZ-RL optimal for production-grade, safety-critical DC-DC and motor control modules.
Availability
ADP3624ARHZ-RL is available at Aetrix Electronics and suitable for AC-to-DC switch mode power supplies, synchronous buck converters, and industrial DC-DC modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for ADP3624ARHZ-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA, with design centers and manufacturing facilities worldwide.
The ADP362x family was developed specifically for high-efficiency, high-frequency power conversion systems - emphasizing fast switching, thermal resilience, and seamless integration with digital controllers in server, telecom, and industrial power supplies.
FAQ
What is the maximum operating junction temperature for ADP3624ARHZ-RL?
The ADP3624ARHZ-RL has an absolute maximum junction temperature of +150°C. Its overtemperature shutdown activates at 150°C–180°C (typical 165°C), with 30°C hysteresis to prevent cycling. Operation up to +125°C ambient is guaranteed, and thermal design must ensure junction temperature remains below 150°C under worst-case load and airflow conditions.
Does ADP3624ARHZ-RL support paralleling of its two output channels?
Yes, ADP3624ARHZ-RL supports parallel operation: INA and INB are tied together as a single input, and OUTA and OUTB are connected to drive one high-current MOSFET gate. This configuration doubles peak drive current to ±8 A and halves per-channel power dissipation - confirmed in Figure 25 of the datasheet and validated for use with gate resistances ≤5 Ω.
What is the function of the OTW pin on ADP3624ARHZ-RL?
The OTW (Overtemperature Warning) pin on ADP3624ARHZ-RL is an open-drain, active-low output that asserts when die temperature reaches 120°C–150°C (typical 135°C). It provides early thermal margin indication before shutdown occurs, allowing host systems to reduce load or throttle frequency - and supports wire-OR'ing with other ADP362x devices for centralized thermal monitoring.
Can ADP3624ARHZ-RL drive high-side N-MOSFETs?
No, ADP3624ARHZ-RL is a dedicated low-side driver only. Its outputs are referenced to PGND and lack bootstrap or charge-pump circuitry required for high-side N-MOSFET gate biasing. It is designed exclusively for ground-referenced N-channel switches - use ADP3623/ADP3633 variants for inverting configurations or complementary drivers for half-bridge topologies.
What decoupling capacitor is recommended for ADP3624ARHZ-RL VDD?
A 4.7 µF low-ESR ceramic capacitor (MLCC) placed adjacent to the VDD and PGND pins is mandatory for ADP3624ARHZ-RL. A 100 nF ceramic capacitor should be added in parallel for high-frequency noise suppression. Both capacitors must be routed with minimal trace length and inductance - improper decoupling risks increased rise times, resonance on OUTA/OUTB, and potential device damage due to VDD ringing.
ADP3624ARHZ-RL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Low-Side
- Channel Type:
- Independent
- Number of Drivers:
- 2
- Gate Type:
- N-Channel MOSFET
- Voltage - Supply:
- 4.5V ~ 18V
- Logic Voltage - VIL, VIH:
- 0.8V, 2V
- Current - Peak Output (Source, Sink):
- 4A, 4A
- Input Type:
- Non-Inverting
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- 10ns, 10ns
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-MSOP-EP
ADP3624ARHZ-RL FAQ
1.How can I place an order for ADP3624ARHZ-RL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP3624ARHZ-RL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP3624ARHZ-RL reliable?
The price and inventory of ADP3624ARHZ-RL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP3624ARHZ-RL is usually 5 days.
3.What payment methods are accepted for ADP3624ARHZ-RL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP3624ARHZ-RL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP3624ARHZ-RL?
ADP3624ARHZ-RL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP3624ARHZ-RL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP3624ARHZ-RL?
For technical support, including ADP3624ARHZ-RL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP3624ARHZ-RL requirements.
6.How does Aetrix verify that ADP3624ARHZ-RL is sourced from the original manufacturer or authorized distributors?
All ADP3624ARHZ-RL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP3624ARHZ-RL meets industry standards.
7.What is the process for return or replacement of ADP3624ARHZ-RL?
All ADP3624ARHZ-RL units undergo pre-shipment inspection (PSI). If there is an issue with ADP3624ARHZ-RL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP3624ARHZ-RL part is unused and in its original packaging.
Return procedure for ADP3624ARHZ-RL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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