Analog Devices Inc. ADP3654ARHZ-R7
- Part No.:
- ADP3654ARHZ-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Gate Drivers
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Datasheet:
-
ADP3654ARHZ-R7.pdf
- Description:
- IC GATE DRVR LOW-SIDE 8MINISOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP3654ARHZ-R7 from Analog Devices is a dual-channel, high-speed, 4 A peak current MOSFET driver in an 8-lead MINI_SO_EP package, designed to drive two independent N-channel power MOSFETs in low-side configurations. It operates from 4.5 V to 18 V, delivers 10 ns typical rise/fall times at 2.2 nF load, and features matched propagation delays (≤2 ns) and precise UVLO with 0.3 V hysteresis - enabling robust startup/shutdown in DC-to-DC converters and synchronous rectifiers.
For engineers reviewing the ADP3654ARHZ-R7 datasheet, ADP3654ARHZ-R7 pinout, ADP3654ARHZ-R7 application, or ADP3654ARHZ-R7 equivalent, key selection criteria include its 4 A peak source/sink capability, −40°C to +125°C junction temperature rating, thermally enhanced MINI_SO_EP package (θJA = 43°C/W), and compatibility with 3.3 V logic inputs driving high-voltage power stages.
Technical Context
The ADP3654ARHZ-R7 implements dual independent low-side gate drivers with internal pull-downs on INA/INB inputs, ensuring MOSFETs remain off during floating input conditions. Its UVLO circuit monitors VDD with 4.2 V turn-on and 3.9 V turn-off thresholds (25°C), providing hysteresis for noise-immune power sequencing when interfacing with low-voltage digital controllers.
Each channel delivers matched propagation delays (tD1 ≤ 30 ns, tD2 ≤ 35 ns) and fast switching (tRISE/tFALL ≤ 25 ns @ 2.2 nF), optimized for high-frequency operation up to several hundred kHz. The device supports parallel operation of both outputs to increase effective drive strength while maintaining thermal performance via its exposed pad (EPAD) connected to PGND.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 4.5 V to 18 V - enables direct use with common intermediate bus voltages (e.g., 5 V, 12 V) without level-shifting. |
| Peak Output Current | ±4 A - sufficient to rapidly charge/discharge large gate capacitances (e.g., >10 nF) in <25 ns. |
| Rise/Fall Time | 10 ns typical @ 2.2 nF - ensures minimal switching overlap loss in synchronous buck or half-bridge topologies. |
| Propagation Delay Matching | ≤2 ns between channels - critical for minimizing shoot-through risk in dual-phase or interleaved power stages. |
| UVLO Threshold Hysteresis | 0.3 V - prevents oscillation during brown-out conditions and guarantees clean power-up/down sequencing. |
| Operating Junction Temp | −40°C to +125°C - validated for industrial and automotive under-hood environments without derating. |
| Input Logic Compatibility | 3.3 V CMOS/TTL - interoperable with FPGA, microcontroller, and digital PWM controller outputs without external buffers. |
Pinout & Package
The ADP3654ARHZ-R7 is housed in an 8-lead MINI_SO_EP package (RH-8-1) with an exposed thermal pad (EPAD) electrically tied to the die substrate (PGND reference). This package provides θJA = 43°C/W on JEDEC 4-layer board, supporting higher power density than SOIC_N_EP in space-constrained designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 8 NC | No Connect | Unbonded pins - must be left floating or grounded per layout best practice; no internal connection. |
| 2 INA | Channel A Input | 3.3 V-compatible digital control signal input; internal pull-down ensures OFF-state default if un-driven. |
| 3 PGND | Power Ground | Low-inductance return path for output currents; must be tightly coupled to MOSFET source and EPAD. |
| 4 INB | Channel B Input | Independent logic-level input for second channel; identical electrical behavior to INA. |
| 5 OUTB | Channel B Output | High-current low-side gate drive output; capable of ±4 A peak into capacitive loads. |
| 6 VDD | Power Supply | Main bias rail (4.5–18 V); requires local 4.7 µF MLCC + 100 nF ceramic bypass to PGND. |
| 7 OUTA | Channel A Output | Matched-output driver with same timing and current specs as OUTB; supports parallel operation. |
| 9 EPAD | Exposed Thermal Pad | Electrically connected to die substrate (PGND); must be soldered to PCB ground plane for thermal and EMI performance. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Independent Low-Side Drivers | Enables separate control of two N-MOSFETs in synchronous rectification or dual-phase DC-DC stages without cross-talk. |
| Matched Propagation Delays | ≤2 ns inter-channel skew ensures precise timing alignment critical for zero-voltage switching (ZVS) and phase-shifted topologies. |
| UVLO with Hysteresis | Guarantees safe disablement below 3.9 V and reliable enablement above 4.2 V, preventing partial turn-on during supply ramp-up. |
| Thermally Enhanced MINI_SO_EP | 43°C/W junction-to-ambient thermal resistance allows sustained 4 A peak drive at +125°C ambient in compact layouts. |
| Parallelable Outputs | INA/INB tied and OUTA/OUTB tied increases effective drive current to ~8 A while reducing per-channel thermal stress. |
Applications
| AC-to-DC SMPS | DC-to-DC Power Supplies |
|---|---|
Use Scenario: High-efficiency flyback or LLC resonant converter with synchronous rectification using dual N-MOSFETs on secondary side. IC Role / Device Role / Timing Role: Low-side gate driver controlling conduction timing of rectifying MOSFETs synchronized to primary-side switching. Use Value: 10 ns rise/fall times minimize reverse recovery losses in SiC/Si diodes; UVLO ensures safe rectifier disable during AC brown-out. | Use Scenario: Multiphase buck regulator for CPU/GPU core voltage with discrete N-MOSFETs per phase. IC Role / Device Role / Timing Role: Dual-channel driver delivering precisely timed gate signals to high-side and low-side FETs in each phase leg. Use Value: Matched propagation delays (<2 ns) reduce dead-time uncertainty, improving efficiency and thermal balance across phases. |
| Synchronous Rectification | Motor Drives |
Use Scenario: Isolated DC-DC module for telecom or server power where secondary-side efficiency is critical. IC Role / Device Role / Timing Role: Gate driver for dual N-channel MOSFETs replacing Schottky diodes in forward or push-pull topologies. Use Value: 4 A peak sink/source capability enables fast turn-off of large rectifier FETs, reducing body diode conduction time and associated losses. | Use Scenario: Brushless DC (BLDC) motor inverter stage using discrete N-MOSFETs in 3-phase half-bridge configuration. IC Role / Device Role / Timing Role: Low-side driver for three independent legs (using multiple ADP3654ARHZ-R7 devices or paralleled channels). Use Value: −40°C to +125°C rating supports operation in harsh motor environments; 3.3 V input compatibility simplifies interface with MCU-based gate control logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual low-side MOSFET driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5113SDX/NOPB | Higher VDD max (20 V), but slower rise/fall (15 ns typ), no UVLO hysteresis, SOIC-8 (no EPAD) | Lacks thermal performance for sustained 4 A drive at high ambient; less robust sequencing in brown-out conditions | Preferred where cost sensitivity outweighs thermal or sequencing requirements |
| UCC27524ADR | Same 4 A drive, 13 ns rise/fall, but only 12 V max VDD, no integrated UVLO, SOIC-8 (no EPAD) | Requires external UVLO circuitry; limited to lower input voltage rails; higher θJA (~70°C/W) | Selected when operating strictly at ≤12 V and external supervision is already present |
Compared with LM5113SDX/NOPB and UCC27524ADR, the ADP3654ARHZ-R7 offers superior thermal management via its MINI_SO_EP EPAD, built-in UVLO hysteresis for autonomous sequencing, and wider 4.5–18 V supply range - making it optimal for industrial DC-DC and high-reliability synchronous rectifier designs where layout space and supply robustness are constrained.
Availability
ADP3654ARHZ-R7 is available at Aetrix Electronics and suitable for AC-to-DC switch mode power supplies, DC-to-DC power supplies, and synchronous rectification applications requiring stable component supply, RoHS-compliant packaging, and guaranteed long-term availability.
Supply support for ADP3654ARHZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, communications, and power management markets.
The ADP3654 product line delivers high-speed, thermally robust gate drivers optimized for high-frequency, high-efficiency power conversion systems - specifically targeting synchronous rectification, multiphase buck regulators, and isolated DC-DC modules.
FAQ
What is the maximum allowable VDD voltage for the ADP3654ARHZ-R7?
The ADP3654ARHZ-R7 has an absolute maximum VDD rating of +20 V, but its operational supply voltage range is specified from 4.5 V to 18 V. Operation above 18 V is not guaranteed for parametric performance or reliability, and exceeding 20 V may cause permanent damage. Designers should maintain VDD within 4.5 V–18 V and use appropriate overvoltage protection if transient spikes are expected in the system.
Does the ADP3654ARHZ-R7 support parallel operation of its two output channels?
Yes, the ADP3654ARHZ-R7 supports parallel operation: INA and INB are tied together, and OUTA and OUTB are connected to drive a single high-capacitance MOSFET gate. This configuration effectively doubles peak current capability to ~8 A and reduces per-channel thermal load. Layout symmetry and equal trace lengths are essential to ensure balanced current sharing between channels in this mode.
What is the function of the EPAD terminal on the ADP3654ARHZ-R7 package?
On the ADP3654ARHZ-R7, the EPAD (exposed pad) is electrically connected to the die substrate and serves as the internal ground reference (PGND). It is not bonded to any pin but must be soldered to the PCB ground plane to achieve the specified θJA = 43°C/W thermal resistance and to provide low-inductance return paths for high-frequency output currents. Omitting EPAD connection degrades thermal performance and increases switching noise.
Can the ADP3654ARHZ-R7 drive high-side N-channel MOSFETs directly?
No, the ADP3654ARHZ-R7 is configured exclusively as a low-side driver: OUTA and OUTB are referenced to PGND and cannot float above it. Driving high-side N-MOSFETs requires either a dedicated high-side driver with floating supply (e.g., bootstrap or isolated bias), or use of P-channel MOSFETs with the ADP3654ARHZ-R7. Its architecture does not support bootstrap capacitor charging or level-shifting functionality.
How does the UVLO feature of the ADP3654ARHZ-R7 behave across temperature?
The ADP3654ARHZ-R7 UVLO turn-on threshold (VUVLO_ON) varies from 3.8 V to 4.5 V and turn-off threshold (VUVLO_OFF) from 3.5 V to 4.3 V across −40°C to +125°C, maintaining ≥0.3 V hysteresis at all temperatures. Figure 5 in the datasheet confirms monotonic shift with temperature, ensuring consistent sequencing margins in wide-temperature industrial applications without external compensation.
ADP3654ARHZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Low-Side
- Channel Type:
- Independent
- Number of Drivers:
- 2
- Gate Type:
- N-Channel MOSFET
- Voltage - Supply:
- 4.5V ~ 18V
- Logic Voltage - VIL, VIH:
- 0.8V, 2V
- Current - Peak Output (Source, Sink):
- 4A, 4A
- Input Type:
- Non-Inverting
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- 10ns, 10ns
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-MSOP-EP
ADP3654ARHZ-R7 FAQ
1.How can I place an order for ADP3654ARHZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP3654ARHZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP3654ARHZ-R7 reliable?
The price and inventory of ADP3654ARHZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP3654ARHZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP3654ARHZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP3654ARHZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP3654ARHZ-R7?
ADP3654ARHZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP3654ARHZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP3654ARHZ-R7?
For technical support, including ADP3654ARHZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP3654ARHZ-R7 requirements.
6.How does Aetrix verify that ADP3654ARHZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP3654ARHZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP3654ARHZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP3654ARHZ-R7?
All ADP3654ARHZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP3654ARHZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP3654ARHZ-R7 part is unused and in its original packaging.
Return procedure for ADP3654ARHZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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