Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Embedded > Application Specific Microcontrollers

Microchip Technology AT97SC3204-U4A14-20

Name: AT97SC3204-U4A14-20
Brand: Microchip Technology
SKU: AT97SC3204-U4A14-20
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: AT97SC3204-U4A14-20

Manufacturer:: Microchip Technology

Category:: Application Specific Microcontrollers

Package:: 28-TSSOP (0.173", 4.40mm Width)

Datasheet:: AT97SC3204-U4A14-20.pdf

Description:: IC CRYPTO TPM LPC 28TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:660

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

AT97SC3204-U4A14-20 from Microchip Technology (formerly Atmel) is a Trusted Platform Module (TPM) IC compliant with TCG TPM 1.2 and LPC Interface Specification 1.2, featuring an AVR RISC microprocessor, hardware RSA crypto engine (2048-bit signature in 200ms), FIPS 140-2–compliant RNG, and 1756-byte NV user storage. It operates at 3.3V on a 33MHz LPC bus for secure boot and platform authentication in PC motherboards.

For engineers reviewing the AT97SC3204-U4A14-20 datasheet, AT97SC3204-U4A14-20 pinout, AT97SC3204-U4A14-20 application, or AT97SC3204-U4A14-20 equivalent, key selection considerations include LPC interface timing compliance, industrial temperature range (-40°C to +85°C), 40-pin QFN package, TCG 1.2 firmware integration, and hardware-based key storage in internal EEPROM.

Technical Context

The AT97SC3204-U4A14-20 implements a complete TCG-compliant security stack on-die: an 8-bit AVR CPU executes certified firmware, while dedicated crypto hardware accelerates RSA-1024 (40ms) and RSA-2048 (200ms) signing and SHA-1 (20μs/64-byte block). It uses dynamic internal memory management for RSA key caching without host intervention.

LPC interface operation includes LFRAME#, LAD[0:3], LCLK (33MHz), SIRQ via SERIRQ, and power-aware features CLKRUN# and LPCPD#. Physical security circuitry, tamper-resistant layout, and isolated SB3V standby rail support robust platform integrity enforcement in embedded and client computing environments.

Key Specifications

Parameter	Value and Actual Design Meaning
TCG Compliance	Fully compliant with TPM 1.2 and PC Client-specific TIS 1.2 - enables interoperable BIOS/UEFI integration and OS-level attestation.
Crypto Engine	Hardware RSA accelerator: 1024-bit signature in 40ms, 2048-bit in 200ms - meets TCG latency requirements for boot-time key operations.
RNG	FIPS 140-2–certified hardware RNG - provides cryptographically secure entropy for key generation and protocol nonces.
NV Storage	1756 bytes of user-defined non-volatile storage - supports persistent policy objects, certificates, and sealed data without external EEPROM.
Interface	33MHz Low Pin Count (LPC) bus with LAD[0:3], LFRAME#, SERIRQ, CLKRUN#, LPCPD# - matches Intel/AMD chipset LPC timing and power-down protocols.
Supply & Temp	3.3V main supply (VCC), 3.3V standby (SB3V); industrial grade (-40°C to +85°C) - ensures reliability in extended-temperature server and industrial PC designs.
Package	40-pad QFN (6.0 × 6.0 × 0.9 mm, 0.50 mm pitch) - surface-mount compatible with automated PCB assembly and thermal performance suitable for dense motherboard layouts.

Pinout & Package

AT97SC3204-U4A14-20 is packaged in a 40-pad Very-thin Quad Flat No Lead (VQFN) with 0.50 mm pitch, 6.0 mm × 6.0 mm body, and exposed thermal pad. Pin 1 is marked by a dot or beveled corner per JEDEC MO-220 WJJD-2.

Pin/Terminal	Circuit Role	Design Meaning
VCC	Main 3.3V supply	Power domain for core logic and crypto engine; requires local decoupling per layout guidelines.
SB3V	Standby 3.3V supply	Maintains RTC, RNG state, and NV storage during system suspend; isolated from VCC for low-power retention.
LAD0–LAD3	LPC bidirectional data/address lines	Time-multiplexed command/address/data bus; supports burst transfers and TIS-compliant handshake timing.
LCLK	33MHz LPC clock input	Synchronizes all LPC transactions; must meet ±1% frequency tolerance and jitter limits per TIS spec.
LFRAME#	LPC frame strobe	Active-low signal indicating start/end of LPC transaction cycle; defines valid window for LAD sampling.
SERIRQ	Serialized interrupt request	Open-drain bidirectional IRQ line supporting shared interrupt arbitration on LPC bus per ACPI specification.
CLKRUN#	PCI clock run control	Enables dynamic clock gating for power savings in mobile platforms; asserted to resume LPC clock after stop.
LPCPD#	LPC power-down request	Signals host to enter low-power state; triggers internal state retention and voltage monitoring sequence.
GPIO-Express-00	Configurable general-purpose I/O	Assigned to TPM_NV_INDEX_GPIO_00 per firmware mapping; usable for platform-specific status signaling or reset coordination.
GND / NC / NBO / ATest / TestI / TestBI	Ground, no-connect, not-bonded-out, test pins	GND pins provide return paths; NC/NBO pins are unconnected internally; test pins are factory-only and must be left floating in production.

Key Features

Feature	Design Value
Single-chip TPM 1.2 solution	Integrates AVR CPU, crypto engine, RNG, EEPROM, and LPC interface - eliminates external components and reduces BOM count and board space.
Hardware asymmetric cryptography	Dedicated RSA engine delivers deterministic 1024/2048-bit signing latency - avoids software-based timing variability and side-channel exposure.
FIPS 140-2–compliant RNG	On-die entropy source validated to cryptographic standards - enables trusted key generation without external entropy injection or polling delays.
1756-byte NV user storage	Persistent, write-protected memory space accessible only via authenticated TPM commands - secures platform keys, certificates, and sealed data.
LPC interface with CLKRUN#/LPCPD#	Full support for ACPI-compliant power management - allows dynamic clock gating and suspend/resume coordination in mobile and desktop platforms.

Applications

Secure Boot Authentication	Platform Integrity Verification
Use Scenario: Verifying firmware image integrity before UEFI execution during cold boot on x86-64 motherboards. IC Role / Device Role / Timing Role: TPM acts as root-of-trust for measurement and signature validation; performs SHA-1 hashing and RSA-2048 verification within 200ms. Use Value: Prevents unauthorized firmware modification by binding boot measurements to hardware-secured keys stored in internal EEPROM.	Use Scenario: Remote attestation of running OS configuration to cloud-based management services in enterprise endpoint security systems. IC Role / Device Role / Timing Role: Generates cryptographically signed PCR (Platform Configuration Register) quotes using hardware-accelerated RSA signing. Use Value: Enables verifiable proof of system state without exposing sensitive keys - critical for zero-trust network access policies.
Hardware-Bound Key Storage	Industrial PC Secure Firmware Update
Use Scenario: Storing BitLocker encryption keys tied to specific motherboard hardware in Windows desktop deployments. IC Role / Device Role / Timing Role: TPM serves as sealed storage container; keys are encrypted under SRK (Storage Root Key) and bound to PCR values. Use Value: Ensures keys remain inaccessible if drive is moved to another system - enforces hardware-based data confidentiality.	Use Scenario: Authenticating and decrypting firmware updates in ruggedized industrial PCs operating in harsh environments. IC Role / Device Role / Timing Role: Validates ECDSA signatures on update payloads using internal crypto engine and verifies update integrity via SHA-1 acceleration. Use Value: Guarantees firmware authenticity and prevents malicious code injection during field updates - essential for functional safety compliance.

Secure Boot Authentication

Platform Integrity Verification

Use Scenario: Verifying firmware image integrity before UEFI execution during cold boot on x86-64 motherboards.

IC Role / Device Role / Timing Role: TPM acts as root-of-trust for measurement and signature validation; performs SHA-1 hashing and RSA-2048 verification within 200ms.

Use Value: Prevents unauthorized firmware modification by binding boot measurements to hardware-secured keys stored in internal EEPROM.

Use Scenario: Remote attestation of running OS configuration to cloud-based management services in enterprise endpoint security systems.

IC Role / Device Role / Timing Role: Generates cryptographically signed PCR (Platform Configuration Register) quotes using hardware-accelerated RSA signing.

Use Value: Enables verifiable proof of system state without exposing sensitive keys - critical for zero-trust network access policies.

Hardware-Bound Key Storage

Industrial PC Secure Firmware Update

Use Scenario: Storing BitLocker encryption keys tied to specific motherboard hardware in Windows desktop deployments.

IC Role / Device Role / Timing Role: TPM serves as sealed storage container; keys are encrypted under SRK (Storage Root Key) and bound to PCR values.

Use Value: Ensures keys remain inaccessible if drive is moved to another system - enforces hardware-based data confidentiality.

Use Scenario: Authenticating and decrypting firmware updates in ruggedized industrial PCs operating in harsh environments.

IC Role / Device Role / Timing Role: Validates ECDSA signatures on update payloads using internal crypto engine and verifies update integrity via SHA-1 acceleration.

Use Value: Guarantees firmware authenticity and prevents malicious code injection during field updates - essential for functional safety compliance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar TPM 1.2 applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Infineon SLB9665TT2.0	48-pin TQFP package; supports both LPC and SPI interfaces; includes additional debug/test modes per Infineon's TCG-certified firmware stack.	Preferred where SPI interface fallback or enhanced diagnostic access is required; LPC timing behavior differs slightly in CLKRUN# response latency.	Select when dual-interface flexibility or vendor-specific firmware toolchain integration is prioritized over footprint minimization.
Nuvoton NPCT750YAXX	32-pin QFN (5×5 mm); integrated 3.3V regulator; lower max operating temperature (70°C); supports TPM 2.0 firmware upgrade path.	Better suited for cost-sensitive consumer notebooks; lacks industrial temp rating and has reduced NV storage (1024 bytes).	Choose for commercial-grade laptops where future TPM 2.0 migration is planned and thermal margin is sufficient.

Compared with SLB9665TT2.0 and NPCT750YAXX, the AT97SC3204-U4A14-20 offers superior industrial temperature support, larger NV storage, and optimized 40-pin QFN footprint for high-density motherboard layouts - making it ideal for embedded industrial PCs and server baseboard management.

Availability

AT97SC3204-U4A14-20 is available at Aetrix Electronics and suitable for secure boot authentication, platform integrity verification, hardware-bound key storage, and industrial PC secure firmware update applications requiring stable component supply across long-lifecycle deployments.

Supply support for AT97SC3204-U4A14-20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel security products including the AT97SC3204 series. The company specializes in microcontrollers, analog, and security ICs for industrial, automotive, and communications markets.

The AT97SC3204 product line was designed as a turnkey TPM 1.2 solution for PC and embedded platform manufacturers needing certified hardware root-of-trust - integrating firmware, crypto acceleration, and LPC interface compliance into a single die.

FAQ

What is the operating temperature range for AT97SC3204-U4A14-20?

The AT97SC3204-U4A14-20 is rated for industrial temperature operation from -40°C to +85°C. This range is confirmed in the Atmel ordering information addendum and supported by thermal characterization in the summary datasheet. The device uses separate SB3V standby rail and thermal-aware layout to maintain TCG-compliant functionality across this full range. AT97SC3204-U4A14-20 is therefore suitable for deployment in uncontrolled-environment industrial PCs and edge servers.

Does AT97SC3204-U4A14-20 support TPM 2.0 firmware?

No, AT97SC3204-U4A14-20 implements only TPM 1.2 functionality as defined in the TCG Main Specification Parts 1–3 and PC Client TIS 1.2. Its firmware, crypto engine, and command set are fixed to version 1.2. AT97SC3204-U4A14-20 does not support TPM 2.0 algorithms, structures, or command extensions. Migration to TPM 2.0 requires hardware replacement with a newer-generation module such as Microchip's ATTPM20 series.

What package type is used for AT97SC3204-U4A14-20?

AT97SC3204-U4A14-20 is supplied in a 40-pad Very-thin Quad Flat No Lead (VQFN) package, designated 40ML1, with 6.0 mm × 6.0 mm body, 0.50 mm pitch, and 0.9 mm maximum height. This is explicitly stated in the "Ordering Information" section and illustrated in Package Drawing 4.2 of the summary datasheet. The part number suffix "U4A14-20" corresponds to this QFN variant.

How much non-volatile storage does AT97SC3204-U4A14-20 provide for user data?

AT97SC3204-U4A14-20 provides 1756 bytes of non-volatile user storage, allocated in the TPM's NV space and accessible via TCG-defined commands like TPM_NV_DefineSpace and TPM_NV_Write. This capacity is specified in the "Features" section and confirmed in the "Description" paragraph of the summary datasheet. AT97SC3204-U4A14-20 uses internal EEPROM for this storage, eliminating need for external memory.

Is AT97SC3204-U4A14-20 RoHS compliant?

Yes, AT97SC3204-U4A14-20 is lead-free and RoHS compliant, as confirmed in the "Ordering Information" table which states "Lead-free, RoHS" for all package variants including the 40ML1 QFN. The device meets EU Directive 2011/65/EU requirements, and packaging materials are documented in Atmel's compliance declarations archived under document ID Atmel-5295ES.

AT97SC3204-U4A14-20 Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: CryptoController™

Package/Case:: 28-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Applications:: Trusted Platform Module (TPM)

Core Processor:: AVR

Program Memory Type:: EEPROM

Controller Series:: -

RAM Size:: -

Interface:: LPC

Number of I/O:: -

Voltage - Supply:: 3.3V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-TSSOP

AT97SC3204-U4A14-20 FAQ

1.How can I place an order for AT97SC3204-U4A14-20 through Aetrix?

Please submit a Request for Quotation (RFQ) for AT97SC3204-U4A14-20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT97SC3204-U4A14-20 reliable?

The price and inventory of AT97SC3204-U4A14-20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3204-U4A14-20 is usually 5 days.

3.What payment methods are accepted for AT97SC3204-U4A14-20?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3204-U4A14-20 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT97SC3204-U4A14-20?

AT97SC3204-U4A14-20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT97SC3204-U4A14-20 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT97SC3204-U4A14-20?

For technical support, including AT97SC3204-U4A14-20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3204-U4A14-20 requirements.

6.How does Aetrix verify that AT97SC3204-U4A14-20 is sourced from the original manufacturer or authorized distributors?

All AT97SC3204-U4A14-20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3204-U4A14-20 meets industry standards.

7.What is the process for return or replacement of AT97SC3204-U4A14-20?

All AT97SC3204-U4A14-20 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3204-U4A14-20, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT97SC3204-U4A14-20 part is unused and in its original packaging.

Return procedure for AT97SC3204-U4A14-20:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…