Microchip Technology AT97SC3204-X4A13-20
- Part No.:
- AT97SC3204-X4A13-20
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT97SC3204-X4A13-20.pdf
- Description:
- IC CRYPTO TPM LPC 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,764
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT97SC3204-X4A13-20 from Microchip Technology (formerly Atmel) is a Trusted Platform Module (TPM) IC compliant with TCG TPM 1.2 and PC Client TIS 1.2 specifications. It integrates an AVR RISC microprocessor, hardware RSA crypto engine (2048-bit signature in 200ms), FIPS 140-2–compliant RNG, 1756-byte NV user storage, and 33MHz LPC interface for secure PC platform authentication and key management.
For engineers reviewing the AT97SC3204-X4A13-20 datasheet, AT97SC3204-X4A13-20 pinout, AT97SC3204-X4A13-20 application, or AT97SC3204-X4A13-20 equivalent, this page delivers verified technical context, package-specific pin mapping, real-world use cases, and validated alternative options for OEM motherboard and embedded security design.
Technical Context
The AT97SC3204-X4A13-20 implements a complete TCG-compliant TPM stack on-die, including dedicated cryptographic acceleration for RSA-1024 (40ms) and RSA-2048 (200ms), SHA-1 (20μs/64-byte block), and internal EEPROM-based key storage. Its LPC interface supports SIRQ and CLKRUN# for power-aware interrupt handling and clock gating in mobile platforms.
It features a hardened physical security architecture with tamper-resistant layout, secure firmware boot, and dynamic internal memory management for RSA keys-requiring no host intervention for key cache maintenance beyond standard TCG commands like TPM_FlushSpecific and TPM_LoadKey2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TCG Compliance | Fully compliant with TPM 1.2 and PC Client TIS 1.2 specifications-enables interoperable secure boot and attestation in Windows/Linux enterprise environments. |
| Crypto Engine | Hardware-accelerated RSA-2048 signature generation in ≤200ms-reduces host CPU load and enables timely attestation during POST and OS startup. |
| RNG | FIPS 140-2–certified hardware random number generator-provides cryptographically secure entropy for key generation and protocol nonces. |
| LPC Interface | 33MHz Low Pin Count bus with LAD[0:3], LFRAME#, LCLK, SERIRQ, and CLKRUN#-directly interfaces with Intel/AMD chipset LPC controllers without bridge logic. |
| Supply Voltage | 3.3V nominal with SB3V standby rail-supports standard PC platform power domains and low-power suspend states. |
| NV Storage | 1756 bytes of user-definable non-volatile storage-enables persistent storage of credentials, certificates, or policy data across reboots and power cycles. |
| Operating Range | -40°C to +85°C industrial grade-qualified for deployment in ruggedized motherboards, industrial PCs, and edge servers. |
Pinout & Package
AT97SC3204-X4A13-20 is packaged in a 40-pad QFN (6.0mm × 6.0mm, 0.50mm pitch), per ordering code X4A13 indicating the 40ML1 variant. This package supports fine-pitch routing and thermal dissipation suitable for dense motherboard layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Main power supply input | 3.3V core supply; must be decoupled locally to meet noise immunity requirements for cryptographic operations. |
| SB3V | Standby power rail | Provides backup power to retain volatile state and enable wake-from-suspend functionality via LPCPD#. |
| LAD0–LAD3 | LPC bidirectional data/address lines | Time-multiplexed command, address, and data transfer over 4-bit LPC bus; requires pull-up resistors per TIS spec. |
| LCLK | LPC clock input | 33MHz system clock sourced from chipset; defines timing for all LPC transactions and internal crypto timing reference. |
| SERIRQ | Serialized interrupt request | Open-drain shared interrupt line supporting multiple LPC devices; used for asynchronous event signaling (e.g., PCR updates). |
| CLKRUN# | PCI clock run control | Enables dynamic clock gating during idle periods-critical for power savings in mobile and fanless platforms. |
| LPCPD# | LPC power-down input | Asserted by host to place device in low-power retention mode while preserving NV state and secure context. |
| GPIO-Express-00 | General-purpose I/O | Configurable as TPM_NV_INDEX_GPIO_00 per TCG specification-supports platform-specific GPIO-controlled security policies. |
Key Features
| Feature | Design Value |
|---|---|
| Single-chip TPM 1.2 solution | Integrates CPU, crypto engine, RNG, EEPROM, and LPC interface-eliminates external firmware dependencies and reduces BOM count. |
| Hardware asymmetric crypto engine | Offloads RSA-1024/2048 signing and verification from host CPU-ensures deterministic latency for measured boot and remote attestation. |
| FIPS 140-2–compliant RNG | Delivers certified entropy for key derivation and protocol randomness-meets NIST SP 800-90A requirements without software seeding. |
| Dynamic internal key cache | Automatically manages up to 16 RSA key slots in SRAM/EEPROM-no host driver intervention required beyond standard TCG commands. |
| Secure hardware layout | Physically hardened die design with meshed power rails and sensor networks-resists fault injection, probing, and side-channel analysis. |
Applications
| Desktop Motherboard Security | Industrial Embedded Control |
|---|---|
Use Scenario: Secure boot and firmware integrity verification on x86-based desktop motherboards during POST and UEFI initialization. IC Role / Device Role / Timing Role: TPM root-of-trust enforcing PCR extension and sealed storage before OS loader execution. Use Value: Enables BitLocker encryption binding and Windows Hello attestation-prevents unauthorized firmware modification and cold-boot attacks. | Use Scenario: Secure credential storage and hardware-based authentication in programmable logic controllers (PLCs) and HMIs operating in harsh environments. IC Role / Device Role / Timing Role: Tamper-resistant key vault and runtime attestation agent interfacing via LPC-to-PCIe bridge or direct LPC controller. Use Value: Supports -40°C to +85°C operation and maintains cryptographic state across brownouts-ensures continuity of secure communication in factory automation. |
| Server Platform Integrity | Medical Device Authentication |
Use Scenario: Remote attestation and secure firmware update validation in rack-mounted servers with IPMI and BMC integration. IC Role / Device Role / Timing Role: Cryptographic co-processor providing signed measurement logs and sealed keys to BMC over LPC. Use Value: Enables zero-touch provisioning and compliance with HIPAA/FDA cybersecurity guidance for firmware integrity assurance. | Use Scenario: Patient data encryption key protection and device identity binding in FDA-cleared diagnostic imaging equipment. IC Role / Device Role / Timing Role: Hardware-enforced identity anchor storing manufacturer-signed certificates and audit logs in NV storage. Use Value: Meets IEC 62304 Class C software safety requirements by isolating key material from application processor memory space. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM 1.2 security module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon SLB9665TT2.0 | Same TCG TPM 1.2 compliance; uses ARM-based core instead of AVR; supports SPI interface in addition to LPC. | Broader interface flexibility but requires different driver stack; lacks GPIO-Express-00 pin assignment. | Select when SPI interface support or ARM ecosystem alignment is prioritized over pin-level compatibility. |
| Nuvoton NPCT650KBAX | TPM 1.2 compliant; integrated 8051 core; supports both LPC and eSPI; includes additional hardware watchdog and voltage monitor. | Targeted at newer eSPI-based platforms; higher pin count (48-pin QFN); not drop-in compatible with 40-pin QFN footprint. | Choose for next-gen designs migrating from LPC to eSPI, especially where enhanced platform monitoring is required. |
Compared with SLB9665TT2.0 and NPCT650KBAX, the AT97SC3204-X4A13-20 offers proven LPC-only integration with minimal footprint and deterministic crypto latency-ideal for cost-sensitive, space-constrained legacy and industrial PC designs requiring field-proven TPM 1.2 functionality.
Availability
AT97SC3204-X4A13-20 is available at Aetrix Electronics and suitable for desktop motherboard security, industrial embedded control, server platform integrity, and medical device authentication requiring stable component supply and long-term lifecycle support.
Supply support for AT97SC3204-X4A13-20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel security products. The company specializes in microcontrollers, analog, and secure authentication solutions for industrial, automotive, and computing markets.
The AT97SC3204-X4A13-20 belongs to Atmel's Trusted Platform Module product line, designed specifically to deliver certified hardware-rooted trust for PC-class and embedded systems requiring TCG-compliant secure boot, attestation, and key management.
FAQ
What is the primary function of the AT97SC3204-X4A13-20 in a computing platform?
The AT97SC3204-X4A13-20 serves as a hardware-based root of trust implementing the TCG TPM 1.2 specification. It performs cryptographic operations-including RSA signing, SHA-1 hashing, and secure random number generation-to enable secure boot, platform attestation, sealed storage, and key management. Its integration into the LPC bus allows direct, low-overhead interaction with the host chipset, making the AT97SC3204-X4A13-20 essential for establishing hardware-enforced security boundaries in desktop, server, and embedded systems.
Does the AT97SC3204-X4A13-20 support both commercial and industrial temperature ranges?
Yes, the AT97SC3204-X4A13-20 is qualified for industrial operation from -40°C to +85°C, as confirmed by Atmel's ordering information and package documentation. This rating applies specifically to the X4A13 variant (40ML1 QFN package), enabling reliable deployment in extended-temperature environments such as factory automation, outdoor kiosks, and medical equipment-unlike commercial-grade variants limited to 0°C–70°C.
How does the AT97SC3204-X4A13-20 handle power management during system suspend states?
The AT97SC3204-X4A13-20 supports low-power operation via its SB3V standby rail and LPCPD# (LPC Power-Down) input. When asserted by the host, LPCPD# places the device in retention mode while preserving NV storage and cryptographic context. Combined with CLKRUN# support, it enables dynamic clock gating-allowing the AT97SC3204-X4A13-20 to maintain secure state with minimal current draw during S3/S4 sleep states in mobile and fanless platforms.
What cryptographic accelerations are implemented in hardware within the AT97SC3204-X4A13-20?
The AT97SC3204-X4A13-20 includes dedicated hardware accelerators for RSA-1024 (40ms signature), RSA-2048 (200ms signature), and SHA-1 (20μs per 64-byte block). These are implemented in fixed-function logic-not software-executed routines-ensuring deterministic latency and resistance to timing side-channel attacks. The AT97SC3204-X4A13-20 does not accelerate AES or ECC; its crypto scope is strictly aligned with TCG TPM 1.2 requirements.
Is the AT97SC3204-X4A13-20 pin-compatible with other Atmel TPM variants such as the 28-pin TSSOP versions?
No, the AT97SC3204-X4A13-20 is not pin-compatible with 28-pin TSSOP variants (e.g., AT97SC3204-28X1). It uses a 40-pad QFN (40ML1) package with distinct pin assignments-including dedicated SERIRQ, CLKRUN#, and GPIO-Express-00 pins not present in the 28-pin layout. PCB layout, decoupling, and signal routing must be designed specifically for the 40ML1 footprint; migration requires board revision and firmware validation.
AT97SC3204-X4A13-20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- CryptoController™
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- LPC
- Number of I/O:
- -
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
AT97SC3204-X4A13-20 FAQ
1.How can I place an order for AT97SC3204-X4A13-20 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3204-X4A13-20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3204-X4A13-20 reliable?
The price and inventory of AT97SC3204-X4A13-20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3204-X4A13-20 is usually 5 days.
3.What payment methods are accepted for AT97SC3204-X4A13-20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3204-X4A13-20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT97SC3204-X4A13-20?
AT97SC3204-X4A13-20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3204-X4A13-20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3204-X4A13-20?
For technical support, including AT97SC3204-X4A13-20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3204-X4A13-20 requirements.
6.How does Aetrix verify that AT97SC3204-X4A13-20 is sourced from the original manufacturer or authorized distributors?
All AT97SC3204-X4A13-20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3204-X4A13-20 meets industry standards.
7.What is the process for return or replacement of AT97SC3204-X4A13-20?
All AT97SC3204-X4A13-20 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3204-X4A13-20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3204-X4A13-20 part is unused and in its original packaging.
Return procedure for AT97SC3204-X4A13-20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT97SC3204-X4A13-20 Tags

-
CYPD3175-24LQXQ
Infineon Technologies

-
SLB9672VU20FW1523XTMA1
Infineon Technologies

-
SLB9670VQ20FW785XTMA1
Infineon Technologies

-
SLB9672XU20FW1523XTMA1
Infineon Technologies

-
SLB9673XU20FW2613XTMA1
Infineon Technologies

-
CYPD3125-40LQXIT
Infineon Technologies

-
AT97SC3204-U2A1A-20
Microchip Technology

-
AT97SC3204-U2A1A-10
Microchip Technology

-
SLM9670AQ20FW1311XTMA1
Infineon Technologies

-
SLB9672XU20FW1613XTMA1
Infineon Technologies

-
SLB9672AU20FW1613XTMA1
Infineon Technologies

-
SLB9673AU20FW2613XTMA1
Infineon Technologies
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
