Microchip Technology AT97SC3205T-G3M46-20
- Part No.:
- AT97SC3205T-G3M46-20
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
AT97SC3205T-G3M46-20.pdf
- Description:
- FF COM I2C TPM 4X4 32VQFN SEK -
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT97SC3205T-G3M46-20 from Atmel is a TCG-compliant Trusted Platform Module (TPM) 1.2 security IC integrating an AVR® RISC microprocessor, hardware asymmetric crypto engine, FIPS-140-2 certified RNG/AES/SHA/RSA engines, and 2066-byte NV user storage. It operates at 3.3V with I²C interface (400kHz Fast Mode) and targets secure boot, platform integrity verification, and key management in embedded computing systems.
For engineers reviewing the AT97SC3205T-G3M46-20 datasheet, AT97SC3205T-G3M46-20 pinout, AT97SC3205T-G3M46-20 application, or AT97SC3205T-G3M46-20 equivalent, this page delivers verified package mapping (32-pin QFN), confirmed I²C timing constraints, TPM-specific GPIO assignments (PP/GPIO, GPIO-Express-00), low-power sleep recovery via TWI_Wakeup#, and FIPS-140-2 module certification scope.
Technical Context
The AT97SC3205T-G3M46-20 implements the full TCG TPM 1.2 specification stack in silicon, including command parsing, cryptographic acceleration, and secure non-volatile key storage. Its AVR CPU executes firmware that enforces strict physical and logical security boundaries between host-accessible registers and protected crypto operations.
It uses dedicated hardware blocks for SHA-1, HMAC, AES-128, RSA-2048, and a FIPS-140-2 validated pseudo-random number generator. The device supports both Standard (100kHz) and Fast (400kHz) I²C modes with precise SM_DAT/SM_CLK pull-up recommendations (800Ω and 1.5kΩ respectively) to ensure reliable communication under noise-sensitive conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TCG Compliance | TPM 1.2 specification fully implemented - enables interoperable trusted boot and attestation across Windows/Linux platforms. |
| I²C Interface Speed | 400kHz Fast Mode / 100kHz Standard Mode - requires specific pull-up values (800Ω on SM_DAT, 1.5kΩ on SM_CLK) for stable high-speed operation. |
| Supply Voltage | 3.3V ±5% - mandates tight decoupling: 2200–4700pF capacitors within 5mm of each VCC pin and 0.1μF at VCC node <10mm from device. |
| FIPS Certification | FIPS-140-2 Level 2 certified module - covers RNG, HMAC, AES, SHA, and RSA engines; validates cryptographic integrity for government and enterprise use. |
| NV Storage Capacity | 2066 bytes user-defined data space - persistent storage for credentials, policies, or custom keys outside standard TPM NV indices. |
| Operating Temperature | −40°C to +85°C industrial range - qualified for deployment in ruggedized embedded systems without thermal derating. |
| Package Type | 32-pad QFN (4.0×4.0×0.90 mm, 0.40 mm pitch) - exposes GND center pad internally tied to ground; supports compact PCB layout and thermal dissipation. |
Pinout & Package
AT97SC3205T-G3M46-20 is packaged in a 32-pad Very Thin QFN (32M3) with 4.0×4.0 mm body, 0.40 mm pitch, and exposed GND center pad internally connected to system ground. Pin assignment follows TCG-compliant TPM I/O mapping with dedicated physical presence (PP/GPIO), express GPIO (GPIO-Express-00), tamper detection (TestBI/GPIO/XTAMPER), and low-power wakeup (TWI_Wakeup#) signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply input | 3.3V main supply requiring localized decoupling (2200–4700pF within 5mm) and global 0.1μF bypass near VCC node. |
| GND | System ground reference | Multiple GND pins plus internal substrate pad tied to ground - critical for noise immunity and RNG stability. |
| SM_DAT / SM_CLK | I²C bidirectional data/clock | Supports 400kHz Fast Mode only with verified pull-ups (800Ω/1.5kΩ); duty cycle near 50% improves timing margin. |
| PP/GPIO | Hardware physical presence indicator | Active-high signal used to assert physical access authorization; internal pull-down allows floating when unused. |
| GPIO-Express-00 | TPM_NV_INDEX_GPIO_00 mapped I/O | Internal pull-up enabled; serves as XOR chain output during I/O test mode; default configured as input. |
| TWI_Wakeup# | Low-power sleep recovery trigger | Two active-low pins must be pulsed simultaneously to exit deep sleep state initiated by TPM_DeepSleep command. |
| TestBI/GPIO/XTAMPER | Multi-function terminal | Configurable as XTAMPER (tamper detection) or GPIO; if unused, tie to GND via 4.7kΩ resistor. |
| PIRQ# | SPI interrupt request output | Open-drain active-low interrupt signal to host processor; tie to GND via 4.7kΩ if not used. |
Key Features
| Feature | Design Value |
|---|---|
| Single-chip TPM 1.2 solution | Integrates AVR CPU, crypto accelerators, EEPROM key storage, and I²C interface - eliminates external components and reduces BOM count. |
| FIPS-140-2 Level 2 certification | Covers RNG, HMAC, AES, SHA, and RSA engines - satisfies U.S. federal and enterprise security policy requirements for cryptographic modules. |
| Secure hardware layout | Dedicated physical security circuitry and masked metal layers prevent side-channel leakage and fault injection attacks. |
| Dynamic key cache management | Hardware-managed RSA key storage with automatic eviction - no host firmware intervention required for TPM_FlushSpecific or TPM_LoadKey2. |
| Low-power deep sleep mode | Automatically entered during idle periods; recoverable via dual TWI_Wakeup# pulse - extends system power budget in battery-constrained designs. |
Applications
| Server Platform Integrity | Industrial Control Secure Boot |
|---|---|
Use Scenario: Verifying firmware authenticity and measuring BIOS/UEFI boot sequence before OS load in rack-mounted servers. IC Role / Device Role / Timing Role: TPM 1.2 root-of-trust anchor performing SHA-1 hashing of PCR registers and signing attestations with embedded RSA-2048 keys. Use Value: Prevents unauthorized firmware modification and enables remote attestation using FIPS-140-2 certified crypto engines. | Use Scenario: Securing PLC firmware updates and authenticating field operator credentials in factory automation systems. IC Role / Device Role / Timing Role: Hardware-enforced credential vault and physical presence gatekeeper (PP/GPIO) for privileged operations. Use Value: Ensures only authorized personnel can initiate firmware reflash, leveraging industrial temperature range (−40°C to +85°C) and robust I²C interface. |
| Embedded Edge Gateway Security | Medical Device Data Integrity |
Use Scenario: Protecting IoT gateway identity and encrypting telemetry before transmission to cloud infrastructure. IC Role / Device Role / Timing Role: Cryptographic co-processor generating AES session keys and signing sensor data payloads via HMAC-SHA1. Use Value: Offloads crypto processing from host MCU while maintaining 2066-byte NV storage for device-specific certificates and keys. | Use Scenario: Ensuring audit log integrity and protecting patient data encryption keys in diagnostic imaging equipment. IC Role / Device Role / Timing Role: Tamper-resistant key store with TestBI/GPIO/XTAMPER support for environmental tamper detection. Use Value: Meets HIPAA and IEC 62304 requirements through FIPS-140-2 certified RNG and secure NV storage of cryptographic material. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM 1.2 security applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon SLB9665TT2.0 | Same TCG TPM 1.2 compliance, 32-pin QFN package, but uses SPI interface instead of I²C; lacks AVR CPU and internal EEPROM key storage. | Requires host-side key management and SPI-capable controller; better suited for high-throughput host processors with SPI peripherals. | Select SLB9665TT2.0 when SPI interface is preferred and host handles key lifecycle; AT97SC3205T-G3M46-20 retains advantage in I²C-only systems and integrated key storage. |
| NXP PCF5102A | TPM 2.0 compliant, 32-pin QFN, supports SHA-256 and ECC; no FIPS-140-2 certification for RNG/crypto engines; different I²C address and command set. | Enables post-TPM 1.2 features like algorithm agility and enhanced attestation, but requires firmware redesign and validation effort. | Choose PCF5102A for new designs targeting TPM 2.0 roadmap; retain AT97SC3205T-G3M46-20 for legacy TPM 1.2 compatibility and FIPS-140-2 assurance. |
Compared with Infineon SLB9665TT2.0 and NXP PCF5102A, the AT97SC3205T-G3M46-20 uniquely combines I²C interface, on-chip AVR CPU, FIPS-140-2 certified crypto engines, and 2066-byte user NV storage - making it optimal for resource-constrained embedded systems requiring drop-in TPM 1.2 functionality with minimal host software overhead.
Availability
AT97SC3205T-G3M46-20 is available at Aetrix Electronics and suitable for server platform integrity verification, industrial control secure boot, and embedded edge gateway security requiring stable component supply and long-term lifecycle support.
Supply support for AT97SC3205T-G3M46-20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and security ICs for embedded applications.
The AT97SC3205T product line delivers certified TPM 1.2 functionality in single-chip form for integration into PCs, servers, industrial controllers, and medical devices where hardware-rooted trust and cryptographic assurance are mandatory.
FAQ
What is the primary interface protocol supported by the AT97SC3205T-G3M46-20?
The AT97SC3205T-G3M46-20 supports only the I²C interface, operating at 100kHz Standard Mode or 400kHz Fast Mode. It does not support SPI or LPC interfaces. Pull-up resistors of 800Ω on SM_DAT and 1.5kΩ on SM_CLK are recommended for reliable 400kHz operation, and the SM_CLK duty cycle should be as close to 50% as possible to maximize timing margin. This interface design simplifies integration into microcontroller-based systems with limited peripheral options.
Does the AT97SC3205T-G3M46-20 include on-chip non-volatile storage for user data?
Yes, the AT97SC3205T-G3M46-20 provides 2066 bytes of dedicated NV storage space for user-defined data, separate from standard TPM NV indices. This space is implemented in internal EEPROM and persists across power cycles. It is accessible via TCG-compliant commands and intended for storing device-specific credentials, configuration policies, or custom keys - all protected by the same FIPS-140-2 certified security boundary applied to RSA key storage.
How is physical presence asserted on the AT97SC3205T-G3M46-20?
Physical presence is asserted via the PP/GPIO pin on the AT97SC3205T-G3M46-20, which functions as a hardware indicator with internal pull-down resistance. When driven high by an external switch or GPIO, it signals authorized physical access to enable privileged TPM operations such as clearing ownership or changing platform configuration. The pin defaults to GPIO input mode and must remain floating or pulled low when unused, per the datasheet guidance.
What certifications apply to the cryptographic engines inside the AT97SC3205T-G3M46-20?
The AT97SC3205T-G3M46-20 is certified as a FIPS-140-2 Level 2 cryptographic module, covering its hardware random number generator (RNG), HMAC, AES-128, SHA-1, and RSA-2048 engines. This certification validates implementation correctness, resistance to physical attack, and operational integrity under defined environmental conditions. The RNG specifically meets FIPS 140-2 Annex C requirements for entropy sources and deterministic random bit generation.
Can the AT97SC3205T-G3M46-20 enter a low-power state, and how is it recovered?
Yes, the AT97SC3205T-G3M46-20 automatically enters low-power sleep mode when idle. Recovery requires pulsing both TWI_Wakeup# pins (pins 7 and 22 in TSSOP, or corresponding terminals in QFN) active-low simultaneously - a unique dual-signal requirement to prevent spurious wakeups. This mechanism is triggered by the TPM_DeepSleep command and documented in the Atmel TPM Specific Commands reference. The AT97SC3205T-G3M46-20 does not support SPI-based wakeup or autonomous timer-based resume.
AT97SC3205T-G3M46-20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- I2C
- Number of I/O:
- 4
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (4x4)
AT97SC3205T-G3M46-20 FAQ
1.How can I place an order for AT97SC3205T-G3M46-20 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3205T-G3M46-20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3205T-G3M46-20 reliable?
The price and inventory of AT97SC3205T-G3M46-20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3205T-G3M46-20 is usually 5 days.
3.What payment methods are accepted for AT97SC3205T-G3M46-20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3205T-G3M46-20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT97SC3205T-G3M46-20?
AT97SC3205T-G3M46-20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3205T-G3M46-20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3205T-G3M46-20?
For technical support, including AT97SC3205T-G3M46-20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3205T-G3M46-20 requirements.
6.How does Aetrix verify that AT97SC3205T-G3M46-20 is sourced from the original manufacturer or authorized distributors?
All AT97SC3205T-G3M46-20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3205T-G3M46-20 meets industry standards.
7.What is the process for return or replacement of AT97SC3205T-G3M46-20?
All AT97SC3205T-G3M46-20 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3205T-G3M46-20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3205T-G3M46-20 part is unused and in its original packaging.
Return procedure for AT97SC3205T-G3M46-20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT97SC3205T-G3M46-20 Tags

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CYPD3175-24LQXQ
Infineon Technologies

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SLB9672VU20FW1523XTMA1
Infineon Technologies

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SLB9670VQ20FW785XTMA1
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SLB9672XU20FW1523XTMA1
Infineon Technologies

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SLB9673XU20FW2613XTMA1
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CYPD3125-40LQXIT
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AT97SC3204-U2A1A-20
Microchip Technology

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AT97SC3204-U2A1A-10
Microchip Technology

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SLM9670AQ20FW1311XTMA1
Infineon Technologies

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SLB9672XU20FW1613XTMA1
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SLB9672AU20FW1613XTMA1
Infineon Technologies

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SLB9673AU20FW2613XTMA1
Infineon Technologies
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