Microchip Technology AT97SC3205T-H3M46-10
- Part No.:
- AT97SC3205T-H3M46-10
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
AT97SC3205T-H3M46-10.pdf
- Description:
- FF IND I2C TPM 4X4 32VQFN SEK -
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT97SC3205T-H3M46-10 from Microchip (formerly Atmel) is a TCG-compliant Trusted Platform Module (TPM) 1.2 security IC integrating an AVR® RISC microprocessor, hardware asymmetric crypto engine, FIPS-140-2 certified RNG/AES/SHA/RSA engines, and 2066-byte NV user storage. It operates at 3.3V with I²C interface (400 kHz Fast Mode) and targets secure boot, platform authentication, and key management in embedded computing systems.
For engineers reviewing the AT97SC3205T-H3M46-10 datasheet, AT97SC3205T-H3M46-10 pinout, AT97SC3205T-H3M46-10 application, or AT97SC3205T-H3M46-10 equivalent, this page delivers verified electrical specs, validated I²C timing constraints, confirmed GPIO-Express and Physical Presence pin functions, package-specific pin mapping for 32-pad QFN, and real-world TPM deployment considerations including deep-sleep recovery via TWI_Wakeup# and PIRQ# interrupt signaling.
Technical Context
The AT97SC3205T-H3M46-10 implements the full TCG TPM 1.2 specification stack in silicon, with dedicated hardware acceleration for RSA key generation, HMAC-SHA-1 signing, and AES-128 encryption. Its internal EEPROM stores persistent RSA keys, while the FIPS-140-2 certified RNG feeds cryptographic primitives and protocol randomness requirements.
It uses a single-chip architecture combining AVR CPU core, SRAM, crypto engine, and physical security circuitry - eliminating external memory dependencies. The I²C interface supports both Standard (100 kHz) and Fast (400 kHz) modes with strict pull-up resistor guidance (800 Ω on SM_DAT, 1.5 kΩ on SM_CLK) and 50% duty-cycle clock optimization for stable communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TCG Compliance | TPM 1.2 specification fully implemented per TCG Main Specification Parts 1–3; enables standardized platform integrity attestation and sealed storage. |
| I²C Interface Speed | 400 kHz Fast Mode / 100 kHz Standard Mode; requires specific pull-up values (SM_DAT: 800 Ω, SM_CLK: 1.5 kΩ) for reliable high-speed operation. |
| Crypto Engines | FIPS-140-2 certified RNG, HMAC, AES-128, SHA-1, and RSA (1024/2048-bit); hardware-accelerated to offload host CPU during key operations. |
| NV Storage | 2066 bytes of user-defined non-volatile storage; mapped via TPM_NV_INDEX_GPIO_00 and other indices for custom data persistence. |
| Supply Voltage | 3.3 V ±10%; requires localized decoupling: 2200–4700 pF capacitors <5 mm from each VCC–GND pair, plus 0.1 µF at VCC node <10 mm from device. |
| Operating Temperature | Industrial range: −40°C to +85°C; validated for continuous operation in extended-temperature embedded platforms without derating. |
| Package | 32-pad QFN (32M3), 4.0 × 4.0 × 0.90 mm body, 0.40 mm pitch; exposed thermal pad tied internally to GND. |
Pinout & Package
AT97SC3205T-H3M46-10 is supplied in a 32-pad Very Thin QFN (32M3) package with 0.40 mm pitch and 4.0 × 4.0 mm body. The exposed center pad is internally connected to GND and may be left floating or soldered to PCB ground plane for thermal and EMI performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply input | 3.3 V main supply; requires dedicated decoupling per datasheet layout rules to prevent noise-induced TPM state corruption. |
| GND | Ground reference | System ground return; multiple GND pins provide low-impedance paths for digital and analog sections; center pad is GND-connected. |
| SM_DAT / SM_CLK | I²C bidirectional data / clock | Standard I²C interface pins; SM_DAT must use 800 Ω pull-up, SM_CLK 1.5 kΩ pull-up for 400 kHz operation; 50% duty cycle improves stability. |
| GPIO-Express-00 | Configurable NV-mapped GPIO | Maps to TPM_NV_INDEX_GPIO_00; internal pull-up enabled; used for user-defined state retention or hardware handshake signals. |
| PP/GPIO | Physical Presence indicator | Hardware-level assertion of physical presence (active-high); required for privileged TPM commands like Clear or Owner establishment. |
| TWI_Wakeup# | Low-power sleep recovery | Active-low signal pair (pins 7 & 22) required to exit deep-sleep mode after TPM_DeepSleep command execution. |
| PIRQ# | Interrupt request output | Open-drain active-low interrupt to host processor; signals pending TPM events (e.g., command completion, error conditions). |
| TestBI/GPIO/XTAMPER | Multi-function terminal | Configurable as XTAMPER (tamper detection) or GPIO; if unused, tie to GND via 4.7 kΩ resistor to avoid floating inputs. |
Key Features
| Feature | Design Value |
|---|---|
| Single-chip TPM 1.2 solution | Integrates CPU, crypto engines, EEPROM, RNG, and physical security logic - eliminates external components and reduces BOM count. |
| FIPS-140-2 certification | Covers RNG, HMAC, AES, SHA, and RSA engines; satisfies regulatory requirements for government and enterprise-grade secure boot and attestation. |
| Hardware Physical Presence (PP) | Dedicated PP/GPIO pin enforces hardware-gated access to sensitive TPM commands, preventing remote privilege escalation. |
| Deep-sleep power management | TPM_DeepSleep command reduces current draw significantly; recovery requires coordinated TWI_Wakeup# pulse sequence - extends system battery life. |
| GPIO-Express architecture | Pre-mapped NV index (TPM_NV_INDEX_GPIO_00) enables deterministic, persistent GPIO state storage across reboots without host software overhead. |
Applications
| Secure Boot Authentication | Platform Integrity Attestation |
|---|---|
Use Scenario: Verifying firmware signature and measuring boot sequence before OS load in industrial gateways. IC Role / Device Role / Timing Role: TPM acts as root-of-trust anchor; measures BIOS, bootloader, and kernel hashes into Platform Configuration Registers (PCRs). Use Value: Prevents unauthorized firmware modification by cryptographically binding boot measurements to hardware-bound RSA keys stored in internal EEPROM. | Use Scenario: Reporting runtime system state to remote management servers in cloud infrastructure servers. IC Role / Device Role / Timing Role: TPM generates signed PCR quotes using its FIPS-certified RSA engine and SHA-1 hash module. Use Value: Enables verifiable proof of unaltered system configuration - critical for compliance audits and zero-trust network access control. |
| Hardware-Bound Key Storage | Physical Presence-Gated Operations |
Use Scenario: Storing disk encryption keys for self-encrypting SSDs in medical imaging devices. IC Role / Device Role / Timing Role: TPM serves as secure key vault; encrypts/decrypts keys using AES-128 and RSA-2048 engines with keys never exposed outside die. Use Value: Ensures data confidentiality even if storage media is physically removed - meets HIPAA and IEC 62304 data-at-rest requirements. | Use Scenario: Enabling owner clear or dictionary attack lockout in kiosk terminals after tampering detection. IC Role / Device Role / Timing Role: PP/GPIO pin asserts hardware presence; TestBI/GPIO/XTAMPER detects enclosure breach; both feed physical security circuitry. Use Value: Blocks sensitive TPM operations unless physical access is confirmed - prevents remote reset or credential extraction attacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM 1.2 security module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon SLB9665TT2.0 | Same TCG TPM 1.2 compliance; SPI interface instead of I²C; 32-pin QFN but different pinout and no GPIO-Express-00 mapping. | Requires SPI host controller; lacks direct NV-mapped GPIO for state persistence; supports higher temperature grade (−40°C to +105°C). | Select when SPI interface is preferred and extended temperature operation is needed; redesign required due to non-pin-compatible interface and GPIO architecture. |
| Nuvoton NPCT750A | TPM 1.2 compliant; I²C interface at 400 kHz; includes integrated voltage supervisor and watchdog; no FIPS-140-2 certification for full module. | Offers enhanced system monitoring features; suitable for cost-sensitive industrial controllers where full FIPS validation is not mandated. | Choose for added system supervision capability and lower unit cost; verify RNG and crypto engine certification scope matches application security policy. |
Compared with AT97SC3205T-H3M46-10, SLB9665TT2.0 shifts interface dependency to SPI and removes GPIO-Express functionality, while NPCT750A trades FIPS-140-2 module certification for integrated supervision - making AT97SC3205T-H3M46-10 optimal for I²C-based designs requiring auditable, hardware-enforced key lifecycle control.
Availability
AT97SC3205T-H3M46-10 is available at Aetrix Electronics and suitable for secure boot authentication, platform integrity attestation, and hardware-bound key storage requiring stable component supply across industrial and embedded computing programs.
Supply support for AT97SC3205T-H3M46-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and qualification for legacy Atmel security ICs including the AT97SC3205T series.
The AT97SC3205T belongs to Atmel's Trusted Platform Module product line, designed specifically to deliver certified, single-chip TPM 1.2 functionality for embedded systems needing hardware-rooted trust without external crypto co-processors.
FAQ
What is the primary interface type and speed supported by the AT97SC3205T-H3M46-10?
The AT97SC3205T-H3M46-10 uses an I²C interface supporting both Standard Mode (100 kHz) and Fast Mode (400 kHz). For reliable 400 kHz operation, the datasheet specifies 800 Ω pull-up on SM_DAT and 1.5 kΩ on SM_CLK, with strong recommendation for a 50% duty-cycle clock waveform to maximize signal integrity and reduce communication errors in noisy environments. The AT97SC3205T-H3M46-10 does not support SPI or UART interfaces.
Does the AT97SC3205T-H3M46-10 include FIPS-140-2 certification, and what modules are covered?
Yes, the AT97SC3205T-H3M46-10 is FIPS-140-2 certified as a complete module, covering its hardware random number generator (RNG), HMAC, AES-128, SHA-1, and RSA cryptographic engines. This certification validates the implementation against NIST standards for cryptographic module security and is documented in the official FIPS certificate issued to Atmel's TPM solution. The AT97SC3205T-H3M46-10 certification applies to the full device, not just individual blocks.
How is physical presence enforced on the AT97SC3205T-H3M46-10, and why is it required?
The AT97SC3205T-H3M46-10 enforces physical presence through the dedicated PP/GPIO pin, which must be driven high to authorize privileged operations such as TPM_Clear, Owner establishment, or dictionary attack lockout reset. This hardware gating prevents remote attackers from executing destructive or privilege-escalating commands without local physical access. The AT97SC3205T-H3M46-10 design mandates this signal for TCG-compliant TPM 1.2 behavior and cannot bypass it via firmware or configuration.
What NV storage capacity and addressing method does the AT97SC3205T-H3M46-10 provide for user data?
The AT97SC3205T-H3M46-10 provides 2066 bytes of non-volatile user storage accessible via TCG-defined NV indices. One dedicated index, TPM_NV_INDEX_GPIO_00, maps directly to the GPIO-Express-00 pin for persistent state retention. User data is written and read using standard TPM_NV_Write and TPM_NV_Read commands, with access controlled by authorization policies. The AT97SC3205T-H3M46-10 does not expose this storage as a generic EEPROM block - all access is mediated by the TPM command interface.
Can the AT97SC3205T-H3M46-10 enter low-power states, and how is wake-up managed?
Yes, the AT97SC3205T-H3M46-10 supports deep-sleep mode via the TPM_DeepSleep command, reducing power consumption during idle periods. Recovery requires pulsing two dedicated pins - TWI_Wakeup# (pin 7) and TWI_Wakeup# (pin 22) - both low simultaneously. This dual-signal requirement prevents accidental wake-up and ensures deterministic resumption. The AT97SC3205T-H3M46-10 does not support automatic wake-up on I²C traffic or timer events - explicit hardware signaling is mandatory.
AT97SC3205T-H3M46-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- I2C
- Number of I/O:
- 4
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (4x4)
AT97SC3205T-H3M46-10 FAQ
1.How can I place an order for AT97SC3205T-H3M46-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3205T-H3M46-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3205T-H3M46-10 reliable?
The price and inventory of AT97SC3205T-H3M46-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3205T-H3M46-10 is usually 5 days.
3.What payment methods are accepted for AT97SC3205T-H3M46-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3205T-H3M46-10 transactions.
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AT97SC3205T-H3M46-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3205T-H3M46-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3205T-H3M46-10?
For technical support, including AT97SC3205T-H3M46-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3205T-H3M46-10 requirements.
6.How does Aetrix verify that AT97SC3205T-H3M46-10 is sourced from the original manufacturer or authorized distributors?
All AT97SC3205T-H3M46-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3205T-H3M46-10 meets industry standards.
7.What is the process for return or replacement of AT97SC3205T-H3M46-10?
All AT97SC3205T-H3M46-10 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3205T-H3M46-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3205T-H3M46-10 part is unused and in its original packaging.
Return procedure for AT97SC3205T-H3M46-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT97SC3205T-H3M46-10 Tags

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CYPD3175-24LQXQ
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SLB9673AU20FW2613XTMA1
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