Microchip Technology AT97SC3205T-U3A1C10B
- Part No.:
- AT97SC3205T-U3A1C10B
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT97SC3205T-U3A1C10B.pdf
- Description:
- FF IND I2C TPM 4.4MM TSSOP UEK
- Quantity:
- Payment:

- Shipping:

Inventory:193
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Product details
Overview
AT97SC3205T-U3A1C10B from Microchip (acquired Atmel) is a TCG-compliant Trusted Platform Module (TPM) 1.2 security IC integrating an AVR® RISC microprocessor, hardware asymmetric crypto engine, FIPS-140-2 certified RNG/AES/SHA/RSA engines, and 2066-byte NV user storage. It operates at 3.3V with I²C interface (400kHz Fast Mode) and targets secure boot, platform authentication, and key management in embedded computing systems.
For engineers reviewing the AT97SC3205T-U3A1C10B datasheet, AT97SC3205T-U3A1C10B pinout, AT97SC3205T-U3A1C10B application, or AT97SC3205T-U3A1C10B equivalent, this page delivers verified package mapping (28-pin TSSOP), confirmed I²C timing constraints, GPIO-Express-00 and PP/GPIO functional roles, low-power TWI_Wakeup# recovery behavior, and FIPS-140-2 module certification scope - all critical for TPM integration validation and supply chain continuity planning.
Technical Context
The AT97SC3205T-U3A1C10B implements the full TCG TPM 1.2 specification stack in silicon, including command parsing, cryptographic acceleration, and secure non-volatile key storage. Its internal architecture combines an 8-bit AVR CPU with dedicated crypto co-processors for RSA, SHA-1, HMAC, and AES, plus a FIPS-140-2 validated random number generator used for key generation and protocol randomness.
Communication occurs exclusively via I²C (SM_DAT/SM_CLK), supporting both Standard (100kHz) and Fast Mode (400kHz) with strict pull-up resistor recommendations (800Ω on SM_DAT, 1.5kΩ on SM_CLK) and 50% duty-cycle optimization for clock stability. The device enters automatic low-power sleep when idle and recovers only upon dual active-low assertion of TWI_Wakeup# pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TCG Compliance | Full TPM 1.2 specification implementation per Trusted Computing Group standards - enables interoperable trusted boot and attestation in PC and embedded platforms. |
| Crypto Engines | FIPS-140-2 certified RNG, HMAC, AES-128, SHA-1, and RSA-2048 - provides hardware-accelerated, tamper-resistant cryptographic operations without host CPU overhead. |
| I²C Interface | 400kHz Fast Mode / 100kHz Standard Mode - requires precise pull-up values (800Ω SM_DAT, 1.5kΩ SM_CLK) and 50% SM_CLK duty cycle for reliable high-speed communication. |
| Supply Voltage | 3.3V ±10% - mandates tight decoupling: 2200–4700pF capacitors <5mm from each VCC-GND pair, plus 0.1μF capacitor <10mm at VCC node junction. |
| NV Storage | 2066 bytes user-defined data space - persistent storage for credentials, certificates, or policy variables independent of host system power state. |
| Operating Temp | Industrial range: −40°C to +85°C - qualified for deployment in ruggedized industrial controllers, network appliances, and edge gateways. |
| Package Options | 28-pin Thin TSSOP (4.4 × 9.7 mm, 0.65 mm pitch) - RoHS-compliant, lead-free, surface-mount compatible with standard reflow profiles. |
Pinout & Package
AT97SC3205T-U3A1C10B is supplied in a 28-pin Thin TSSOP package (4.40 mm × 9.70 mm body, 0.65 mm pitch), RoHS-compliant and lead-free. Pin 1 identification is marked by a notch or dot; substrate center pad is not present in TSSOP variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply Input | 3.3V main supply requiring localized 2200–4700pF decoupling <5mm to adjacent GND; failure causes unreliable crypto operation or reset instability. |
| LRESET# | Active-Low Reset | Pulsing low resets internal TPM state; minimum 2μs pulse width required; must remain asserted until VCC stabilizes at power-up. |
| SM_DAT / SM_CLK | I²C Data/Clock | Bidirectional I²C bus interface; 400kHz operation demands 800Ω pull-up on SM_DAT and 1.5kΩ on SM_CLK; 50% clock duty cycle improves signal integrity. |
| GPIO-Express-00 | TPM-NV Mapped GPIO | Hardwired to TPM_NV_INDEX_GPIO_00; internal pull-up enabled; default input mode; floats if unused - used for platform-specific status signaling. |
| PP/GPIO | Physical Presence Indicator | Hardware physical presence flag (active-high); internal pull-down enabled; floating if unused; required for TCG-compliant admin authorization flows. |
| TWI_Wakeup# | Low-Power Recovery | Two-pin active-low wake signal; both pins must be pulsed low simultaneously to exit deep-sleep mode after TPM_DeepSleep command. |
Key Features
| Feature | Design Value |
|---|---|
| Single-chip TPM 1.2 solution | Integrates CPU, crypto accelerators, RNG, EEPROM, and I²C interface in one die - eliminates external component dependencies and reduces BOM count for secure subsystems. |
| FIPS-140-2 Level 2 certification | Certified module includes RNG, HMAC, AES, SHA, and RSA engines - satisfies U.S. federal and enterprise security procurement requirements without additional validation effort. |
| Hardware asymmetric crypto engine | Accelerates RSA-2048 key generation and signing operations in <100ms - enables fast attestation and secure firmware updates without host CPU bottlenecks. |
| Internal EEPROM for RSA keys | Dedicated non-volatile memory stores multiple RSA key pairs securely - prevents key extraction via side-channel or fault injection attacks during runtime. |
| GPIO-Express-00 and PP/GPIO support | Provides two standardized, TCG-mapped GPIOs for platform-level control - enables hardware-enforced physical presence confirmation and OEM-specific status reporting. |
Applications
| Secure Boot Authentication | Platform Integrity Attestation |
|---|---|
Use Scenario: Verifying firmware signature and measurement integrity before OS load in industrial gateways. IC Role / Device Role / Timing Role: TPM performs SHA-1 hashing of boot ROM and bootloader images, signs results with embedded RSA key, and reports PCR values over I²C. Use Value: Prevents unauthorized firmware execution by cryptographically binding boot sequence to hardware-rooted keys stored in AT97SC3205T-U3A1C10B EEPROM. | Use Scenario: Reporting runtime system measurements to cloud-based security orchestration tools in network infrastructure equipment. IC Role / Device Role / Timing Role: AT97SC3205T-U3A1C10B acts as trusted measurement anchor - captures and signs sensor, configuration, and software state hashes using TPM_Quote command. Use Value: Enables remote verification of device health and compliance status via signed attestations, leveraging FIPS-140-2 certified crypto engines inside AT97SC3205T-U3A1C10B. |
| Hardware-Based Key Management | Physical Presence Enforcement |
Use Scenario: Storing and protecting TLS private keys for encrypted communication in IoT edge nodes. IC Role / Device Role / Timing Role: AT97SC3205T-U3A1C10B generates, stores, and uses RSA-2048 keys internally - never exposes private key material to host processor or memory. Use Value: Mitigates key theft via memory dump or DMA attacks by isolating cryptographic operations and key storage within tamper-resistant silicon of AT97SC3205T-U3A1C10B. | Use Scenario: Requiring hardware-confirmed operator presence before enabling administrative TPM functions (e.g., dictionary attack lockout reset). IC Role / Device Role / Timing Role: PP/GPIO pin serves as TCG-mandated Physical Presence indicator - driven high by front-panel switch to authorize privileged commands. Use Value: Enforces human-in-the-loop authorization for sensitive operations, preventing remote privilege escalation via AT97SC3205T-U3A1C10B's PP/GPIO hardware gating logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM 1.2 security applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST33HTPH2E28A | 28-pin TSSOP, 3.3V, TPM 1.2, FIPS-140-2 Level 2 certified, but uses SPI interface instead of I²C. | Requires SPI-capable host controller and different driver stack; lacks GPIO-Express-00 mapping; supports same industrial temp range. | Select when host design already implements SPI-based TPM support and board layout accommodates different pinout and timing constraints. |
| SLB9670TT20I | 32-pin QFN, 3.3V, TPM 2.0 compliant, FIPS-140-2 Level 3 certified, includes enhanced countermeasures and larger NV space (4KB). | Not backward-compatible with TPM 1.2 command set; requires firmware update and host stack migration; supports newer TCG protocols like TPM 2.0 PolicySession. | Select for new designs requiring forward-looking TPM 2.0 features, higher assurance level, and extended lifecycle support beyond AT97SC3205T-U3A1C10B's end-of-life roadmap. |
Compared with ST33HTPH2E28A and SLB9670TT20I, the AT97SC3205T-U3A1C10B offers proven I²C-based TPM 1.2 integration with minimal host driver complexity, GPIO-Express-00 for OEM extensions, and industrial temperature qualification - making it optimal for cost-sensitive, field-deployed embedded systems where TPM 1.2 compliance and long-term supply stability are primary criteria.
Availability
AT97SC3205T-U3A1C10B is available at Aetrix Electronics and suitable for secure boot authentication, platform integrity attestation, and hardware-based key management applications requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for AT97SC3205T-U3A1C10B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains legacy Atmel product lines including security ICs. The company specializes in microcontrollers, analog, FPGA, and secure authentication solutions for industrial, automotive, and communications markets.
The AT97SC3205T-U3A1C10B belongs to Atmel's Trusted Platform Module family, designed specifically to deliver TCG-compliant hardware root-of-trust for embedded systems where firmware integrity, remote attestation, and cryptographic key protection are mission-critical.
FAQ
What is the interface type and speed supported by AT97SC3205T-U3A1C10B?
The AT97SC3205T-U3A1C10B uses an I²C interface supporting both Standard Mode (100kHz) and Fast Mode (400kHz). For reliable 400kHz operation, the datasheet specifies 800Ω pull-up on SM_DAT and 1.5kΩ on SM_CLK, with emphasis on maintaining a 50% duty cycle on SM_CLK to ensure signal integrity. The AT97SC3205T-U3A1C10B does not support SPI or other serial interfaces.
Does AT97SC3205T-U3A1C10B support FIPS-140-2 certification, and what components are covered?
Yes, the AT97SC3205T-U3A1C10B is a FIPS-140-2 Level 2 certified module. Certification explicitly covers the hardware random number generator (RNG), HMAC, AES, SHA, and RSA cryptographic engines - all implemented in dedicated hardware within the device. This certification applies to the complete AT97SC3205T-U3A1C10B module, not just individual blocks, and is documented in the official NIST certificate listing.
What is the purpose of the GPIO-Express-00 pin on AT97SC3205T-U3A1C10B?
The GPIO-Express-00 pin on AT97SC3205T-U3A1C10B is hardwired to TPM_NV_INDEX_GPIO_00 per TCG specification and provides a standardized, non-volatile GPIO interface for OEM use. It features an internal pull-up resistor and defaults to input mode. When unused, it should be left floating. The AT97SC3205T-U3A1C10B uses this pin to enable platform-specific status reporting or control signals without requiring custom firmware extensions.
How does AT97SC3205T-U3A1C10B enter and exit low-power sleep mode?
The AT97SC3205T-U3A1C10B automatically enters low-power sleep when idle. To exit, the host must assert both TWI_Wakeup# pins (pins 7 and 22 in TSSOP) with simultaneous active-low pulses. This dual-pin requirement prevents spurious wake events. If unused, pin 7 may float or tie to GND; pin 22 must be tied to GND or VCC. The AT97SC3205T-U3A1C10B does not support single-pin wake or timer-based wake-up.
What package and temperature grade does AT97SC3205T-U3A1C10B ship in?
The AT97SC3205T-U3A1C10B is offered in a 28-pin Thin TSSOP package (4.40 mm × 9.70 mm body, 0.65 mm pitch) and qualified for industrial temperature range (−40°C to +85°C). The part number suffix "U3A1C10B" specifically denotes the industrial-grade TSSOP variant. It is RoHS-compliant and lead-free, with no-connect pins (e.g., TSSOP pins 5, 12–15, 27–28) that may be tied to VCC, GND, or left floating per design needs.
AT97SC3205T-U3A1C10B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- I2C
- Number of I/O:
- 4
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
AT97SC3205T-U3A1C10B FAQ
1.How can I place an order for AT97SC3205T-U3A1C10B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3205T-U3A1C10B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3205T-U3A1C10B reliable?
The price and inventory of AT97SC3205T-U3A1C10B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3205T-U3A1C10B is usually 5 days.
3.What payment methods are accepted for AT97SC3205T-U3A1C10B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3205T-U3A1C10B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT97SC3205T-U3A1C10B?
AT97SC3205T-U3A1C10B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3205T-U3A1C10B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3205T-U3A1C10B?
For technical support, including AT97SC3205T-U3A1C10B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3205T-U3A1C10B requirements.
6.How does Aetrix verify that AT97SC3205T-U3A1C10B is sourced from the original manufacturer or authorized distributors?
All AT97SC3205T-U3A1C10B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3205T-U3A1C10B meets industry standards.
7.What is the process for return or replacement of AT97SC3205T-U3A1C10B?
All AT97SC3205T-U3A1C10B units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3205T-U3A1C10B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3205T-U3A1C10B part is unused and in its original packaging.
Return procedure for AT97SC3205T-U3A1C10B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT97SC3205T-U3A1C10B Tags

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CYPD3175-24LQXQ
Infineon Technologies

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SLB9672VU20FW1523XTMA1
Infineon Technologies

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SLB9670VQ20FW785XTMA1
Infineon Technologies

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SLB9672XU20FW1523XTMA1
Infineon Technologies

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SLB9673XU20FW2613XTMA1
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CYPD3125-40LQXIT
Infineon Technologies

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AT97SC3204-U2A1A-20
Microchip Technology

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AT97SC3204-U2A1A-10
Microchip Technology

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SLM9670AQ20FW1311XTMA1
Infineon Technologies

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SLB9672XU20FW1613XTMA1
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SLB9672AU20FW1613XTMA1
Infineon Technologies

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SLB9673AU20FW2613XTMA1
Infineon Technologies
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