Microchip Technology AT97SC3205T-X3A13-10
- Part No.:
- AT97SC3205T-X3A13-10
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT97SC3205T-X3A13-10.pdf
- Description:
- TPM I2C C8 REVF COMM 4.4MM TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT97SC3205T-X3A13-10 from Microchip Technology (formerly Atmel) is a TCG-compliant Trusted Platform Module (TPM) 1.2 security IC implementing hardware-based asymmetric cryptography, FIPS-140-2 certified RNG/AES/SHA/RSA engines, and 2066-byte NV user storage. It integrates an AVR® RISC microprocessor and operates at 3.3V via I²C interface in embedded platform root-of-trust applications.
For engineers reviewing the AT97SC3205T-X3A13-10 datasheet, AT97SC3205T-X3A13-10 pinout, AT97SC3205T-X3A13-10 application, or AT97SC3205T-X3A13-10 equivalent, this page delivers verified package mapping (28-pin TSSOP), confirmed I²C timing (400 kHz Fast Mode), validated GPIO-Express-00 and PP/GPIO roles, and FIPS-140-2 module certification scope for secure boot and key management design.
Technical Context
The AT97SC3205T-X3A13-10 implements the full TCG TPM 1.2 specification stack in silicon, including command parsing, cryptographic acceleration, and persistent key storage in internal EEPROM. Its AVR CPU executes firmware that enforces strict physical and logical security boundaries between host I²C transactions and protected crypto operations.
It supports dual-power-state operation with automatic low-power sleep entry and TWI_Wakeup#-triggered recovery, while maintaining FIPS-140-2 validation for RNG entropy, HMAC, AES-128, SHA-1, and RSA-2048 engines - all operating within a tamper-resistant hardware security boundary.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Compliance | TCG TPM Specification Version 1.2 - enables interoperable trusted boot and attestation in PC, server, and industrial control platforms. |
| Crypto Engine | Hardware-accelerated RSA-2048, AES-128, SHA-1, HMAC - offloads host CPU and prevents software-side key exposure during signing/decryption. |
| I²C Interface | 400 kHz Fast Mode / 100 kHz Standard Mode - supports high-throughput command/response cycles with SM_DAT/SM_CLK pull-up guidance (800 Ω / 1.5 kΩ). |
| Supply Voltage | 3.3 V ±10% - requires dedicated decoupling: 2200–4700 pF caps <5 mm from each VCC–GND pair plus 0.1 µF at VCC node. |
| Temperature Range | Industrial: −40°C to +85°C - qualified for deployment in factory automation, edge gateways, and ruggedized embedded systems. |
| NV Storage | 2066 bytes user-defined data space - persists configuration, credentials, or audit logs across power cycles without host intervention. |
Pinout & Package
AT97SC3205T-X3A13-10 is packaged in a 28-pin Thin TSSOP (4.40 mm × 9.70 mm, 0.65 mm pitch) with exposed thermal pad not present. Pin functions are electrically validated per Atmel-8883AS datasheet summary.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply input | 3.3 V main supply requiring localized decoupling; multiple VCC pins enable robust noise immunity in dense PCB layouts. |
| GND | Reference ground | System ground reference for analog/digital domains; adjacent placement to VCC pins required for bypass capacitor routing. |
| LRESET# | Active-low reset | Asynchronous hard reset; minimum 2 µs pulse width; must remain asserted until VCC stabilizes at power-on. |
| SM_DAT / SM_CLK | I²C bidirectional data / clock | Standard I²C interface compliant with TCG TPM 1.2 protocol; supports 400 kHz operation with defined pull-up constraints. |
| PP/GPIO | Physical presence indicator / GPIO | Hardware-enforced physical presence assertion (active-high); defaults to GPIO input with internal pull-down. |
| GPIO-Express-00 | Dedicated NV-mapped GPIO | Maps to TPM_NV_INDEX_GPIO_00; provides persistent state retention and XOR chain output in test mode. |
| TWI_Wakeup# | Low-power wake trigger | Two-pin active-low sequence required to exit deep-sleep; enables zero-power standby with deterministic recovery latency. |
| PIRQ# | Interrupt request output | Open-drain interrupt signal indicating pending TPM response or event; requires external pull-up resistor. |
Key Features
| Feature | Design Value |
|---|---|
| FIPS-140-2 Level 2 Certification | Certified RNG, HMAC, AES, SHA, and RSA engines - satisfies U.S. federal and enterprise security policy requirements for cryptographic integrity. |
| Internal EEPROM Key Storage | Secure nonvolatile storage for RSA private keys - eliminates need for external secure memory and prevents runtime key extraction. |
| Hardware Physical Presence (PP) | Dedicated PP/GPIO pin with tamper-aware logic - enforces operator confirmation before sensitive operations like clearing ownership or disabling TPM. |
| Dynamic Key Cache Management | Automatic loading/unloading of RSA keys using TPM_FlushSpecific and TPM_LoadKey2 - reduces host firmware complexity and memory footprint. |
| XTAMPER Support | TestBI/GPIO/XTAMPER pin implements external tamper detection - enables integration with chassis intrusion sensors or voltage monitors. |
Applications
| Server Secure Boot | Industrial HMI Authentication |
|---|---|
Use Scenario: Verifying firmware integrity during BIOS/UEFI initialization in rack-mounted servers. IC Role / Device Role / Timing Role: Root-of-trust anchor performing SHA-1 hash verification and RSA-2048 signature validation on boot images. Use Value: Prevents unauthorized firmware execution by binding cryptographic keys to hardware identity and enforcing measured boot chains. | Use Scenario: Authenticating operator credentials and encrypting session keys in programmable logic controller HMIs. IC Role / Device Role / Timing Role: Secure credential vault and AES-128 session key generator interfaced via I²C to ARM Cortex-M host. Use Value: Enables role-based access control with cryptographically bound identities, eliminating plaintext password storage in flash. |
| Edge Gateway Device Identity | Medical IoT Data Integrity |
Use Scenario: Establishing unique, unclonable device identity for TLS mutual authentication in cellular-connected edge gateways. IC Role / Device Role / Timing Role: Hardware-bound ECDSA key generation and certificate signing authority for X.509 enrollment. Use Value: Provides cryptographically verifiable device identity resistant to cloning or firmware replay attacks. | Use Scenario: Signing sensor telemetry payloads before transmission from portable diagnostic devices. IC Role / Device Role / Timing Role: Real-time SHA-1 hashing and RSA-2048 signing engine for time-critical patient data streams. Use Value: Ensures end-to-end data provenance and detects tampering in regulated healthcare environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM security module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon SLB9670 | TPM 2.0 compliant; supports SHA-256 and ECC; 32-pin QFN only; no AVR core - uses proprietary secure processor. | Required for Windows 11 compliance and post-2020 OEM platform designs; lacks GPIO-Express-00 and XTAMPER pin functionality. | Select SLB9670 when TPM 2.0 features, ECC acceleration, or Windows 11 readiness are mandatory; AT97SC3205T-X3A13-10 remains optimal for legacy TPM 1.2 deployments with GPIO flexibility. |
| NXP PCF5122 | TPM 1.2 compliant; integrated 32-bit ARM SecurCore SC300; 48-pin LQFP; supports 1.8 V/3.3 V I/O; no FIPS-140-2 certification. | Suitable for mixed-voltage industrial controllers; lacks FIPS validation and NV user storage size (only 512 B). | Choose PCF5122 where ARM-based firmware extensibility and dual-voltage I/O are prioritized over FIPS assurance and larger NV capacity. |
Compared with SLB9670 and PCF5122, AT97SC3205T-X3A13-10 uniquely combines FIPS-140-2 certification, 2066-byte NV user space, and dual-mode GPIO (PP/GPIO, GPIO-Express-00) in a compact 28-pin TSSOP - making it the most suitable choice for cost-sensitive, industrial-grade TPM 1.2 implementations requiring field-programmable tamper response and persistent credential storage.
Availability
AT97SC3205T-X3A13-10 is available at Aetrix Electronics and suitable for server secure boot, industrial HMI authentication, edge gateway device identity, and medical IoT data integrity applications requiring stable component supply and long-term lifecycle support.
Supply support for AT97SC3205T-X3A13-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and qualification for legacy Atmel security ICs.
The AT97SC3205T-X3A13-10 belongs to Atmel's TPM security controller family, designed specifically to deliver certified, single-chip root-of-trust solutions for embedded platforms needing hardware-enforced integrity verification and cryptographic key protection.
FAQ
What is the primary security certification level of the AT97SC3205T-X3A13-10?
The AT97SC3205T-X3A13-10 is FIPS-140-2 Level 2 certified, covering its hardware random number generator (RNG), HMAC, AES-128, SHA-1, and RSA-2048 cryptographic engines. This certification validates the module's resistance to physical tampering and ensures algorithmic correctness under NIST-defined testing protocols. The AT97SC3205T-X3A13-10 achieves this through on-die physical security circuitry and tightly controlled firmware execution paths.
Does the AT97SC3205T-X3A13-10 support both commercial and industrial temperature ranges?
Yes, the AT97SC3205T-X3A13-10 is qualified for industrial operation from −40°C to +85°C, as confirmed in the Atmel-8883AS datasheet summary. It also supports commercial range (0°C to 70°C), but the X3A13-10 suffix specifically denotes the industrial-grade variant. This makes the AT97SC3205T-X3A13-10 suitable for deployment in harsh environments such as factory floors, outdoor gateways, and transportation infrastructure.
How does the AT97SC3205T-X3A13-10 handle low-power operation and wake-up?
The AT97SC3205T-X3A13-10 automatically enters low-power sleep when idle and supports deep-sleep recovery via the TWI_Wakeup# pin pair. Both pins (TSSOP pins 7 and 22) must be pulsed active-low to exit sleep mode. If unused, pin 7 may float or tie to GND; pin 22 must tie to GND or VCC. This dual-signal mechanism prevents spurious wake events and ensures deterministic power-state transitions in the AT97SC3205T-X3A13-10.
What is the function of the PP/GPIO pin on the AT97SC3205T-X3A13-10?
The PP/GPIO pin on the AT97SC3205T-X3A13-10 serves dual roles: as a hardware Physical Presence indicator (active-high) and as a general-purpose input/output. In TPM 1.2 mode, it enforces operator confirmation before sensitive commands like Clear Owner or Disable TPM. Its internal pull-down resistor means it defaults to logic low when floating, and the AT97SC3205T-X3A13-10 firmware interprets high assertion as physical presence confirmation.
Can the AT97SC3205T-X3A13-10 be used in new designs requiring TPM 2.0 compliance?
No, the AT97SC3205T-X3A13-10 implements only TCG TPM Specification Version 1.2 and does not support TPM 2.0 features such as SHA-256, ECC algorithms, or hierarchical key structures. For TPM 2.0 compliance - required by Windows 11 and modern UEFI platforms - designers must select alternatives like the Infineon SLB9670. The AT97SC3205T-X3A13-10 remains appropriate for maintaining legacy TPM 1.2 systems with validated security workflows.
AT97SC3205T-X3A13-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- I2C
- Number of I/O:
- 4
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
AT97SC3205T-X3A13-10 FAQ
1.How can I place an order for AT97SC3205T-X3A13-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3205T-X3A13-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3205T-X3A13-10 reliable?
The price and inventory of AT97SC3205T-X3A13-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3205T-X3A13-10 is usually 5 days.
3.What payment methods are accepted for AT97SC3205T-X3A13-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3205T-X3A13-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT97SC3205T-X3A13-10?
AT97SC3205T-X3A13-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3205T-X3A13-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3205T-X3A13-10?
For technical support, including AT97SC3205T-X3A13-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3205T-X3A13-10 requirements.
6.How does Aetrix verify that AT97SC3205T-X3A13-10 is sourced from the original manufacturer or authorized distributors?
All AT97SC3205T-X3A13-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3205T-X3A13-10 meets industry standards.
7.What is the process for return or replacement of AT97SC3205T-X3A13-10?
All AT97SC3205T-X3A13-10 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3205T-X3A13-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3205T-X3A13-10 part is unused and in its original packaging.
Return procedure for AT97SC3205T-X3A13-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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