Microchip Technology AT97SC3205-X3A12-10
- Part No.:
- AT97SC3205-X3A12-10
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT97SC3205-X3A12-10.pdf
- Description:
- IC CRYPTO TPM 28TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT97SC3205-X3A12-10 from Microchip Technology (acquired Atmel in 2016) is a TCG-compliant Trusted Platform Module (TPM) security IC implementing TPM 1.2 specification with hardware-based RSA crypto engine, FIPS-140-2 certified RNG/AES/SHA/RSA engines, and 2066-byte NV user storage. It serves as a turnkey secure root-of-trust for PC BIOS and embedded platform authentication.
For engineers reviewing the AT97SC3205-X3A12-10 datasheet, AT97SC3205-X3A12-10 pinout, AT97SC3205-X3A12-10 application, or AT97SC3205-X3A12-10 equivalent, key selection factors include SPI interface compliance (TIS v1.3), industrial temperature range (-40°C to +85°C), 3.3V supply, 28-pin thin TSSOP package, and hardware physical presence (PP/GPIO) support.
Technical Context
The AT97SC3205-X3A12-10 integrates an AVR 8-bit RISC CPU with dedicated cryptographic hardware including FIPS-140-2 validated RNG, HMAC, AES-128, SHA-1, and RSA-2048 engines. Its internal EEPROM stores RSA keys and supports TCG-defined NV indices.
It implements the TCG PC Client-Specific TPM Interface Specification (TIS) v1.3 over SPI, with active-low PIRQ# interrupt signaling, SPI_CS# chip select, and SPI_RST# reset control. The module enters low-power state automatically during idle and requires no system intervention for key cache management.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TCG Compliance | TPM 1.2 specification and PC Client-Specific TIS v1.3 - ensures interoperability with standard BIOS and OS TPM stacks |
| Crypto Engines | FIPS-140-2 certified RNG, HMAC, AES-128, SHA-1, RSA-2048 - enables secure key generation, attestation, and sealed storage |
| Interface | SPI up to 45 MHz (typical PC operation: 24–33 MHz) - supports high-speed command/response with standard host controllers |
| Supply Voltage | 3.3 V ±10% - compatible with modern low-voltage motherboard power rails; requires 2200–4700 pF decoupling per VCC pin |
| Operating Temp | -40°C to +85°C - qualified for industrial-grade embedded systems and extended-temperature PC platforms |
| NV Storage | 2066 bytes user-defined data space - sufficient for platform configuration hashes, certificates, and policy blobs |
| Package | 28-pin thin TSSOP (4.4 × 9.7 mm, 0.65 mm pitch) - surface-mount compatible with automated PCB assembly |
Pinout & Package
AT97SC3205-X3A12-10 is packaged in a 28-lead thin TSSOP (4.4 mm × 9.7 mm body, 0.65 mm pitch) with exposed thermal pad not present; all VCC and GND pins require localized decoupling per datasheet layout guidance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply Input | 3.3 V main supply; two pins require individual 2200–4700 pF bypass capacitors placed <5 mm from each VCC–GND pair |
| GND | System Ground Reference | Four dedicated ground pins; critical for noise immunity of crypto operations and RNG stability |
| MISO / MOSI / SPI_CLK / SPI_CS# / SPI_RST# | SPI Bus Interface | Standard 4-wire SPI slave interface; SPI_CS# and SPI_RST# are active-low with 2 μs minimum pulse width for reset |
| PIRQ# | Interrupt Output | Active-low open-drain interrupt signal; must be pulled to GND via 4.7 kΩ if unused |
| PP/GPIO | Hardware Physical Presence | Active-high input indicating physical presence assertion; internal pull-down; tied to system reset per TCG requirements |
| GPIO Express-00 | Configurable GPIO | Maps to TPM_NV_INDEX_GPIO_00; internal pull-up; floats high when unused; used for platform-specific NV access |
| XTamper / TestBI | Tamper Detection Input | Active-high external tamper indicator; shares pin with disabled test function; requires 4.7 kΩ pull-down if unused |
Key Features
| Feature | Design Value |
|---|---|
| FIPS-140-2 Certified Crypto Subsystem | Validated RNG, HMAC, AES-128, SHA-1, and RSA-2048 engines enable NIST-compliant secure boot and remote attestation |
| Integrated AVR RISC CPU + EEPROM Key Store | Dedicated 8-bit processor executes TPM firmware independently; internal EEPROM securely retains RSA keys across power cycles |
| TCG PC Client TIS v1.3 SPI Interface | Guarantees compatibility with industry-standard TPM drivers (e.g., Windows TPM Base Services, Linux tpm_tis) |
| Hardware Physical Presence (PP) Support | PP/GPIO pin enables BIOS-level enforcement of admin-only TPM commands (e.g., Clear, Disable), meeting TCG platform requirements |
| 2066-Byte User NV Storage | Allocatable non-volatile memory space for OEM-specific data (e.g., platform certificates, measured boot logs, policy configurations) |
Applications
| PC BIOS Security | Industrial Embedded Authentication |
|---|---|
Use Scenario: Secure boot chain validation and measured launch in x86 desktop/laptop motherboards. IC Role / Device Role / Timing Role: Root-of-trust security controller executing TPM 1.2 commands via SPI during POST and OS handoff. Use Value: Enables Windows BitLocker encryption, remote attestation, and firmware integrity verification using hardware-bound keys. | Use Scenario: Identity binding and secure firmware update in programmable logic controllers (PLCs) and HMIs. IC Role / Device Role / Timing Role: Tamper-resistant credential store and cryptographic accelerator for TLS handshake and signed OTA updates. Use Value: Prevents unauthorized firmware modification via hardware-enforced signature verification and PP-locked key management. |
| Server Platform Integrity | Medical Device Secure Boot |
Use Scenario: Hypervisor-level attestation and sealed storage in rack-mounted servers with UEFI firmware. IC Role / Device Role / Timing Role: TPM 1.2-compliant security co-processor interfacing with BMC and host CPU via dedicated SPI bus. Use Value: Supports Intel TXT and AMD SVM trusted execution environments by providing cryptographically verifiable platform state measurements. | Use Scenario: Regulatory-compliant boot authentication in FDA-cleared diagnostic imaging equipment. IC Role / Device Role / Timing Role: FIPS-140-2 Level 2 validated security module ensuring cryptographic key protection and audit-log integrity. Use Value: Meets IEC 62304 and HIPAA requirements for secure device identity, encrypted patient data handling, and tamper-evident logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM security applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon SLB9670 | TPM 2.0 compliant; supports ECC and SHA-256; higher SPI clock (up to 66 MHz); different pinout and register map | Required for Windows 11 and newer UEFI platforms mandating TPM 2.0; not backward-compatible with legacy TPM 1.2 stacks | Select SLB9670 only when upgrading to TPM 2.0 infrastructure; AT97SC3205-X3A12-10 remains optimal for TPM 1.2–only deployments. |
| Nuvoton NPCT750 | TPM 1.2 compliant; identical SPI interface and TIS v1.3 support; 32-pin QFN package; lacks hardware PP/GPIO pin | Suitable for space-constrained designs where PP enforcement is handled externally; no native physical presence signaling on-chip | Choose NPCT750 when board layout favors QFN and PP logic is implemented at MCU level; AT97SC3205-X3A12-10 provides integrated PP/GPIO for direct BIOS integration. |
Compared with SLB9670 and NPCT750, the AT97SC3205-X3A12-10 delivers verified TPM 1.2 compliance with on-die physical presence control and industrial temperature support in a mature 28-pin TSSOP footprint-making it ideal for cost-sensitive, long-lifecycle PC and embedded platforms requiring field-proven security without architectural migration.
Availability
AT97SC3205-X3A12-10 is available at Aetrix Electronics and suitable for PC motherboard design, industrial control system integration, and medical device secure boot applications requiring stable component supply and long-term lifecycle assurance.
Supply support for AT97SC3205-X3A12-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT97SC3205 family.
The AT97SC3205 belongs to Atmel's Trusted Platform Module product line, designed specifically to deliver certified, single-chip TPM 1.2 solutions for PC client and embedded platforms requiring hardware-rooted trust and FIPS-validated cryptography.
FAQ
What is the primary compliance standard met by the AT97SC3205-X3A12-10?
The AT97SC3205-X3A12-10 is fully compliant with the Trusted Computing Group (TCG) Trusted Platform Module (TPM) Version 1.2 Specification and the PC Client-Specific TPM Interface Specification (TIS) Version 1.3. It also holds FIPS-140-2 certification for its RNG, HMAC, AES, SHA, and RSA cryptographic engines - confirming its suitability for government and enterprise security applications requiring validated crypto modules.
Does the AT97SC3205-X3A12-10 support hardware physical presence (PP) functionality?
Yes, the AT97SC3205-X3A12-10 includes a dedicated PP/GPIO pin that serves as a hardware physical presence indicator, active-high per TCG requirements. This pin must be tied to system reset to enforce admin-only TPM commands such as Clear or Disable. Its internal pull-down resistor allows safe floating when unused, and the AT97SC3205-X3A12-10 firmware enforces PP state checking before executing sensitive operations.
What are the supported operating temperature and supply voltage ranges for the AT97SC3205-X3A12-10?
The AT97SC3205-X3A12-10 operates across -40°C to +85°C (industrial grade) and is powered by a single 3.3 V ±10% supply. Decoupling is critical: two 2200–4700 pF capacitors must be placed within 5 mm of each VCC–GND pair, and a 0.1 µF capacitor should be located near the VCC node junction. The AT97SC3205-X3A12-10 automatically enters low-power mode during idle periods without software intervention.
How does the AT97SC3205-X3A12-10 handle non-volatile storage for user data?
The AT97SC3205-X3A12-10 provides 2066 bytes of dedicated NV storage space accessible via TCG-defined NV indices. This space is used for platform-specific data such as measurement logs, certificates, and policy configurations. Access is controlled through authenticated TPM commands (e.g., TPM_NV_Write, TPM_NV_Read), and the AT97SC3205-X3A12-10 enforces authorization policies including write-lock and read-lock attributes per index.
What package type and pin count does the AT97SC3205-X3A12-10 use?
The AT97SC3205-X3A12-10 uses a 28-pin thin TSSOP package (4.4 mm × 9.7 mm body, 0.65 mm pitch), designated as "28X1" in Atmel's ordering nomenclature. It features four GND pins, two VCC pins, and dedicated SPI signals (MISO, MOSI, SPI_CLK, SPI_CS#, SPI_RST#), plus PIRQ#, PP/GPIO, GPIO Express-00, and XTamper/TestBI - all electrically and mechanically defined in the official Atmel package drawing 28X1.
AT97SC3205-X3A12-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- AVR
- Program Memory Type:
- EEPROM
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- SPI
- Number of I/O:
- 4
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
AT97SC3205-X3A12-10 FAQ
1.How can I place an order for AT97SC3205-X3A12-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT97SC3205-X3A12-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT97SC3205-X3A12-10 reliable?
The price and inventory of AT97SC3205-X3A12-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT97SC3205-X3A12-10 is usually 5 days.
3.What payment methods are accepted for AT97SC3205-X3A12-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT97SC3205-X3A12-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT97SC3205-X3A12-10?
AT97SC3205-X3A12-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT97SC3205-X3A12-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT97SC3205-X3A12-10?
For technical support, including AT97SC3205-X3A12-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT97SC3205-X3A12-10 requirements.
6.How does Aetrix verify that AT97SC3205-X3A12-10 is sourced from the original manufacturer or authorized distributors?
All AT97SC3205-X3A12-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT97SC3205-X3A12-10 meets industry standards.
7.What is the process for return or replacement of AT97SC3205-X3A12-10?
All AT97SC3205-X3A12-10 units undergo pre-shipment inspection (PSI). If there is an issue with AT97SC3205-X3A12-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT97SC3205-X3A12-10 part is unused and in its original packaging.
Return procedure for AT97SC3205-X3A12-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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