Nexperia USA Inc. BC846S/ZLH

Overview

BC846S from Nexperia is a dual NPN general-purpose transistor in a SOT363-3 (TSSOP6) package, delivering two independent transistors with V_CEO = 65 V, I_C = 100 mA per device, and h_FE ≥ 110 at 2 mA/5 V - used for compact signal amplification and discrete switching in space-constrained PCBs.

For engineers reviewing the BC846S datasheet, BC846S pinout, BC846S application, or BC846S equivalent, this page provides verified pin functions, thermal derating curves, per-transistor limiting values, and validated alternatives for dual-transistor layout optimization.

Technical Context

The BC846S integrates two electrically isolated NPN transistors sharing no internal coupling - enabling independent biasing and operation without crosstalk. Each transistor supports DC current gain ≥110 at 2 mA and maintains V_CEsat ≤ 300 mV at I_C = 100 mA / I_B = 5 mA.

Thermal performance is defined for FR4 PCB mounting: R_th(j-a) = 568 K/W per transistor and 416 K/W per device, with total power dissipation rated at 220 mW per transistor and 300 mW per package at T_amb ≤ 25 °C.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 1.15 mm height, with exposed pad not present - optimized for automated reflow assembly on standard FR4 PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual NPN transistor applications.

Compared with BC846S, BC847S offers higher DC gain for reduced base current but no voltage or power advantage, while MBT3904DW1T1G trades 25 V headroom and 100 mW thermal capacity for lower unit cost in non-industrial applications.

Availability

BC846S is available at Aetrix Electronics and suitable for LED driver circuits, level-shifting interfaces, low-power sensor amplifiers, and redundant signal conditioning requiring stable component supply across automotive infotainment, industrial IoT gateways, and medical wearable platforms.

Supply support for BC846S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and mobile markets.

The BC846S belongs to Nexperia's general-purpose bipolar transistor family, engineered for space-constrained, cost-sensitive applications demanding predictable gain, low saturation voltage, and robust thermal behavior on standard PCBs.

FAQ

What is the maximum allowable junction temperature for BC846S?

The absolute maximum junction temperature (T_j) is 150 °C, as specified in Table 5 of the datasheet. Operation above this value risks permanent degradation of h_FE and increased leakage. Derating begins at T_amb > 25 °C per Fig. 1, with R_th(j-a) = 568 K/W per transistor defining the slope.

Can BC846S be used in linear amplifier configurations?

Yes - its h_FE stability across I_C = 0.1–100 mA (Fig. 3) and low V_CEsat support Class-A and AB small-signal amplification. However, thermal resistance limits continuous dissipation to 220 mW per transistor, requiring careful bias point selection to avoid thermal runaway.

Is the BC846S RoHS-compliant and halogen-free?

Yes - Nexperia confirms BC846S complies with EU RoHS Directive 2011/65/EU and is halogen-free per IEC 61249-2-21, with lead-free matte tin termination and no antimony, bromine, chlorine, fluorine, or iodine compounds above threshold limits.

How does the SOT363-3 package affect soldering process parameters?

The SOT363-3 footprint requires precise stencil design: 0.5 mm × 0.5 mm solder paste pads (4×), 0.6 mm × 0.6 mm solder lands (4×), and 0.4 mm × 0.4 mm fiducials. Reflow peak temperature must not exceed 260 °C for ≤10 seconds to prevent delamination per Fig. 8.