Microchip Technology CEC1736-S0-I/2HW-PROTO2

Overview

CEC1736-S0-I/2HW-PROTO2 from Microchip Technology is a pre-provisioned Real Time Platform Root of Trust Controller implementing NIST 800-193 and OCP Security-compliant Soteria-G3 firmware. It features a 96 MHz ARM Cortex-M4F core, hardware-accelerated P-384 ECDSA, AES-256, SHA-384, SP800-90B TRNG, and SPI Flash monitoring for up to one Application Processor with dual external SPI flash devices - deployed in server boot integrity and telecom platform attestation systems.

For engineers reviewing the CEC1736-S0-I/2HW-PROTO2 datasheet, CEC1736-S0-I/2HW-PROTO2 pinout, CEC1736-S0-I/2HW-PROTO2 application, or CEC1736-S0-I/2HW-PROTO2 equivalent, key selection considerations include 64-pin VFBGA package compatibility, QSPI0-only monitoring capability, 1.8V/3.3V configurable I/O power, fused lifecycle management, and SPDM-compliant component attestation support.

Technical Context

The CEC1736-S0-I/2HW-PROTO2 implements an immutable Boot ROM that loads and authenticates Soteria-G3 firmware from internal flash before enabling secure boot of Application Processor images. Its single QSPI0 interface supports real-time signature verification and opcode-level integrity checking during AP firmware load and runtime execution.

SPI Monitor logic operates in both passive observation and active intervention modes - blocking illegal flash commands (e.g., Chip Erase) before completion using hardware-level signal control. The device integrates a Key Management Engine, PUF-based identity generation, and lockable OTP storage, all gated by fused lifecycle states (development/test/production).

Key Specifications

Pinout & Package

CEC1736-S0-I/2HW-PROTO2 uses a 64-pin Very Thin Fine-Pitch Ball Grid Array (VFBGA) package, 5.5 mm × 5.5 mm × 0.92 mm body, with 0.4 mm ball pitch. This variant supports only QSPI0 (no QSPI1), limiting it to one Application Processor with up to two external SPI flash components.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar platform root of trust applications.

Compared with CEC1736-S0-I/2HW-PROTO2, the 2ZW variant adds QSPI1 support for dual-AP scalability but requires full mechanical redesign, while the CEC1706 offers lower security assurance and no path to Soteria-G3 feature set - making CEC1736-S0-I/2HW-PROTO2 the sole option for new NIST/OCP-compliant single-AP deployments.

Availability

CEC1736-S0-I/2HW-PROTO2 is available at Aetrix Electronics and suitable for server BMC security, telecom baseband unit integrity, and industrial edge gateway trusted boot requiring stable component supply, long-term lifecycle support, and certified firmware provisioning.

Supply support for CEC1736-S0-I/2HW-PROTO2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and security ICs, with global design, manufacturing, and support infrastructure.

The CEC173x TrustFLEX family delivers Real Time Platform Root of Trust Controllers targeting NIST 800-193 and OCP-compliant systems - designed specifically for hardware-enforced secure boot, runtime attestation, and resilient firmware update in servers, telecom, and industrial infrastructure.

FAQ

What security standards does the CEC1736-S0-I/2HW-PROTO2 comply with?

The CEC1736-S0-I/2HW-PROTO2 complies with NIST Special Publication 800-193 (Platform Firmware Resilience) and Open Compute Project (OCP) Security Project requirements. It implements CNSA Suite cryptographic algorithms (P-384 ECDSA, AES-256, SHA-384), SP800-90B TRNG, and SPDM-compliant attestation - all verified in the Soteria-G3 firmware stack shipped pre-provisioned on the device.

Does the CEC1736-S0-I/2HW-PROTO2 support dual Application Processors?

No, the CEC1736-S0-I/2HW-PROTO2 supports only one Application Processor via its single QSPI0 interface. The 2HW package variant lacks QSPI1 signals and associated pins - confirmed by the pinout table showing AP1_RESET# as reserved and unconnected. For dual-AP support, the 84-pin CEC1736-S0-I/2ZW-TFLX must be used instead.

What is the role of the SPI Monitor in the CEC1736-S0-I/2HW-PROTO2?

The SPI Monitor in the CEC1736-S0-I/2HW-PROTO2 performs real-time hash calculation and hardware-level intervention on QSPI0 traffic. It detects violations such as illegal flash commands (e.g., Chip Erase) and blocks them before completion by asserting control over SPI signals - protecting the connected SPI flash from persistent corruption even if the Application Processor is compromised.

Can the CEC1736-S0-I/2HW-PROTO2 perform runtime re-authentication of AP firmware?

Yes, the CEC1736-S0-I/2HW-PROTO2 performs runtime re-authentication of AP firmware images during normal operation. As the Application Processor reads firmware from external SPI flash, the device recalculates image hashes in real time and reports authentication status over the dedicated I²C port - enabling continuous integrity verification beyond initial boot.

How is device identity secured in the CEC1736-S0-I/2HW-PROTO2?

Device identity in the CEC1736-S0-I/2HW-PROTO2 is secured using a hardware-based Physically Unclonable Function (PUF) compliant with SP800-162. The PUF generates a unique, repeatable cryptographic key derived from intrinsic silicon variations - eliminating the need for stored secrets and resisting physical extraction or cloning attacks throughout the device's lifecycle.