Microchip Technology CEC1736-S0-I/2HW-TFLX

Overview

CEC1736-S0-I/2HW-TFLX from Microchip Technology is a Real Time Platform Root of Trust Controller implementing hardware-enforced secure boot (P-384), AES256, SHA-384, ECDSA, and SP800-90B-compliant TRNG for server, telecom, and industrial embedded systems. It features an ARM Cortex-M4F core at 96 MHz, 64-pin VFBGA (5.5×5.5×0.92 mm), and supports secure boot of one Application Processor with dual SPI flash monitoring.

For engineers reviewing the CEC1736-S0-I/2HW-TFLX datasheet, CEC1736-S0-I/2HW-TFLX pinout, CEC1736-S0-I/2HW-TFLX application, or CEC1736-S0-I/2HW-TFLX equivalent, this page delivers verified technical context, exact pin functions, NIST 800-193–compliant security features, and validated alternative parts for platform root-of-trust design in OCP-aligned infrastructure.

Technical Context

The CEC1736-S0-I/2HW-TFLX implements a two-stage immutable root of trust: Boot ROM authenticates Soteria-G3 firmware from internal flash, then Soteria-G3 enforces AP image authentication before releasing AP_RESET#. Its dedicated SPI Monitor block performs real-time signature verification during AP boot and runtime opcode-level integrity checks on QSPI0 traffic only.

This variant integrates hardware crypto acceleration (AES256, SHA-384, ECDSA), PUF-based key generation, lockable OTP memory, and lifecycle management with fused security states. It supports 1.8V or 3.3V I/O operation, light/heavy sleep modes, and uses a single QSPI port (QSPI0) with two chip selects-unlike the 84-pin 2ZW variant which supports dual QSPI ports.

Key Specifications

Pinout & Package

CEC1736-S0-I/2HW-TFLX uses a 64-pin Very Thin Fine-Pitch Ball Grid Array (VFBGA) package, designated 2HW, measuring 5.5 mm × 5.5 mm × 0.92 mm with 0.4 mm ball pitch. This package supports one QSPI interface (QSPI0), two I2C ports (I2C00, I2C10), UART0, SWD/JTAG debug, and 48 GPIOs with configurable alternate functions including reset control, watchdog, and LED signaling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar platform root-of-trust applications.

Compared with CEC1736-S0-I/2HW-TFLX, the 2ZW variant adds hardware support for dual-AP monitoring but increases PCB area and BOM cost; the MAX32590EVKIT requires significant firmware investment and lacks NIST 800-193 certification out-of-box, making it unsuitable for OCP-compliant deployments needing pre-validated security features.

Availability

CEC1736-S0-I/2HW-TFLX is available at Aetrix Electronics and suitable for server BMC, telecom line card, and industrial edge gateway designs requiring stable component supply, long-term lifecycle assurance, and NIST 800-193–compliant platform resiliency.

Supply support for CEC1736-S0-I/2HW-TFLX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and security ICs, with global design centers and ISO 9001-certified manufacturing.

The CEC173x-TFLX product line delivers pre-provisioned, NIST 800-193–compliant Root of Trust controllers for infrastructure equipment, enabling rapid integration of certified secure boot, attestation, and firmware resilience without custom firmware development.

FAQ

What is the primary security function of the CEC1736-S0-I/2HW-TFLX?

The CEC1736-S0-I/2HW-TFLX serves as a Real Time Platform Root of Trust Controller, enforcing hardware-based secure boot of one Application Processor using P-384 cryptography, real-time SPI flash monitoring, and Soteria-G3 firmware. It holds AP0 in reset until authenticated firmware images pass validation, and provides SPDM-compliant attestation over I2C. The CEC1736-S0-I/2HW-TFLX implements these functions with immutable Boot ROM and pre-provisioned firmware, eliminating software-only attack surfaces.

Does the CEC1736-S0-I/2HW-TFLX support dual Application Processors?

No, the CEC1736-S0-I/2HW-TFLX supports only one Application Processor (AP0) via its single QSPI0 interface with two chip selects (QSPI0_IN_CS0# and QSPI0_IN_CS1#). Dual-AP support requires the 84-pin CEC1736-S0-I/2ZW-TFLX variant, which includes QSPI1 signals and dedicated monitoring logic for a second AP domain. Pinout documentation confirms GPIO131/AP1_RESET# is reserved and non-functional in the 2HW package.

What firmware is pre-installed on the CEC1736-S0-I/2HW-TFLX?

The CEC1736-S0-I/2HW-TFLX ships with pre-provisioned Soteria-G3 firmware, certified to MISRA, Coverity®, and CERT® C standards and validated by third-party penetration testing. This firmware implements NIST 800-193–compliant secure boot, SPDM attestation, PLDM-based secure updates, crisis recovery, and key revocation. The Boot ROM loads and authenticates Soteria-G3 from internal flash, establishing an immutable root of trust before any customer code executes.

How does the SPI Monitor feature work on the CEC1736-S0-I/2HW-TFLX?

The CEC1736-S0-I/2HW-TFLX SPI Monitor operates exclusively on the QSPI0 bus, performing real-time signature verification during AP0 boot and opcode-level integrity checks during runtime. It detects violations such as illegal commands (e.g., chip erase) or unauthorized memory accesses, then intervenes by asserting hardware control over QSPI0 signals to cancel the offending transaction before completion. This intervention works with standard 8-pin NOR flash devices and requires no external components.

What package and pin count does the CEC1736-S0-I/2HW-TFLX use?

The CEC1736-S0-I/2HW-TFLX uses a 64-pin Very Thin Fine-Pitch Ball Grid Array (VFBGA) package, designated 2HW, with dimensions of 5.5 mm × 5.5 mm × 0.92 mm and 0.4 mm ball pitch. It contains 48 GPIOs, two I2C interfaces (I2C00 and I2C10), UART0, SWD/JTAG debug, and dedicated QSPI0 monitoring pins - all mapped per Microchip's DS00005397A-page 10 pinout table. The 2HW package excludes QSPI1 signals present in the 84-pin 2ZW variant.