Microchip Technology CEC1736-S0-I/2ZW-PROTO2

Overview

CEC1736-S0-I/2ZW-PROTO2 from Microchip Technology is a Real Time Platform Root of Trust controller featuring an ARM® Cortex-M4F core running at up to 96 MHz, dual SPI Flash monitoring capability, 384 KB SRAM (320 KB code + 64 KB data), and hardware-accelerated cryptography including AES-256, SHA-384, ECDSA, and RSA-4096 - deployed in server BMC/CPU boot integrity protection systems.

For engineers reviewing the CEC1736-S0-I/2ZW-PROTO2 datasheet, CEC1736-S0-I/2ZW-PROTO2 pinout, CEC1736-S0-I/2ZW-PROTO2 application, or CEC1736-S0-I/2ZW-PROTO2 equivalent, key selection criteria include dual-channel SPI flash intervention, TCG DICE compliance, 84-pin WFBGA package with VTR1/VTR2 I/O voltage separation, and fused life cycle security management for production RoT deployment.

Technical Context

The CEC1736-S0-I/2ZW-PROTO2 implements two independent QSPI analog switches and dual SPI Flash monitor blocks - one per host (BMC and CPU) - each with dedicated 64 KB match pattern RAM and real-time hash calculation on 8 KB regions. It enforces runtime SPI access control via regional permission settings and intervenes before illegal erase/write operations complete.

Its secure boot chain leverages immutable Boot ROM (CNSA-compliant SHA-384/ECC384), supports AES-256 encrypted SPI Flash images, and provides SPDM-based attestation via EC_FW. The device operates across -40°C to +85°C with 3.3 V core supply and optional 1.8 V SPI interface voltage, entering Light or Heavy Sleep modes with wake-capable GPIO, timers, and I²C events.

Key Specifications

Pinout & Package

CEC1736-S0-I/2ZW-PROTO2 uses an 84-pin WFBGA package (2ZW variant) with separate VTR1 and VTR2 power domains for dual SPI channel isolation, 3.3 V VTR_REG core supply, and dedicated pins for QSPI0/QSPI1 interfaces, dual LED outputs, UART, JTAG/SWD debug, and tamper-sensing inputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar embedded controller security applications.

Compared with CEC1736-S0-I/2HW, the CEC1736-S0-I/2ZW-PROTO2 adds dual SPI monitoring, 2× flash capacity, and 19 additional GPIOs - enabling full BMC+CPU platform integrity coverage in a single IC. Versus MAX32570, it integrates flash storage, analog isolation, and host-aware intervention logic - reducing BOM count and eliminating external signal routing for flash protection.

Availability

CEC1736-S0-I/2ZW-PROTO2 is available at Aetrix Electronics and suitable for server BMC firmware integrity, telecom baseband RoT, and industrial edge controller secure boot requiring stable component supply and long-term lifecycle support.

Supply support for CEC1736-S0-I/2ZW-PROTO2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company specializing in microcontrollers, analog components, and security ICs for industrial, automotive, and communications markets.

The CEC173x family is designed as Real Time Platform Root of Trust controllers - integrating secure boot, cryptographic acceleration, and active SPI flash monitoring specifically for server, telecom, and embedded computing platforms demanding hardware-enforced firmware integrity.

FAQ

What is the primary security function of the CEC1736-S0-I/2ZW-PROTO2?

The CEC1736-S0-I/2ZW-PROTO2 serves as a hardware-enforced Real Time Platform Root of Trust, performing dual-channel SPI Flash monitoring with active intervention, immutable secure boot via Boot ROM (SHA-384/ECC384), and SPDM-based attestation. Its core function is to verify firmware authenticity during host boot and prevent unauthorized flash modifications during runtime - directly protecting BMC and CPU boot paths in server and telecom systems. This behavior is implemented in the CEC1736-S0-I/2ZW-PROTO2 silicon and cannot be bypassed by software.

Does the CEC1736-S0-I/2ZW-PROTO2 support both 1.8 V and 3.3 V SPI interfaces?

Yes, the CEC1736-S0-I/2ZW-PROTO2 supports dual-voltage SPI operation: its VTR1 and VTR2 I/O banks are independently configurable for either 1.8 V or 3.3 V nominal operation, enabling direct interfacing with mixed-voltage SPI Flash devices used by BMC and CPU subsystems. This capability is confirmed in the DS00004571A datasheet under Operating Conditions and Pin Configuration sections, and applies specifically to the 2ZW package variant used in CEC1736-S0-I/2ZW-PROTO2.

How does the CEC1736-S0-I/2ZW-PROTO2 differ from the CEC1734-S0-I/2ZW variant?

The CEC1736-S0-I/2ZW-PROTO2 features a higher-performance ARM Cortex-M4F core (96 MHz vs. CEC1734's unspecified lower frequency), dual PWM outputs (vs. one in CEC1734), and enhanced tamper detection covering temperature and voltage (CEC1734 omits temperature sensing). Device ID 0024_41_xx h confirms CEC1736 silicon revision, and Table 1-1 explicitly lists CEC1736-S0-I/2ZW with 2× PWM, 71 GPIOs, and full tamper countermeasures - distinguishing it from CEC1734-S0-I/2ZW in CEC1736-S0-I/2ZW-PROTO2's functional scope.

Can the CEC1736-S0-I/2ZW-PROTO2 operate in low-power modes while maintaining security monitoring?

Yes, the CEC1736-S0-I/2ZW-PROTO2 maintains full SPI Flash monitoring and tamper detection functionality in both Light Sleep and Heavy Sleep modes. Its RTOS Timer runs continuously off the 32 kHz oscillator across all sleep states, and SPI monitor blocks remain active - verifying flash accesses and triggering intervention even when the Cortex-M4F core is halted. This ensures uninterrupted firmware integrity enforcement without sacrificing power efficiency in always-on platform security applications.

Is JTAG enabled by default on the CEC1736-S0-I/2ZW-PROTO2?

No, JTAG is disabled by default on the CEC1736-S0-I/2ZW-PROTO2. The GPIO170 pin functions as JTAG_STRAP and must be pulled down at power-up to keep JTAG disabled - a requirement for production security. This behavior is documented in the Pin Naming Conventions section (DS00004571A-page 9) and enforced by Boot ROM initialization. Enabling JTAG requires explicit OTP programming and physical strap modification, aligning with fused life cycle security policies for CEC1736-S0-I/2ZW-PROTO2.