Texas Instruments CP3SP33SMR/NOPB
- Part No.:
- CP3SP33SMR/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Application Specific Microcontrollers
- Package:
- 144-LFBGA
- Datasheet:
-
CP3SP33SMR/NOPB.pdf
- Description:
- IC CPU W/BLUTOOTH&CAN 144-BGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CP3SP33SMR/NOPB from National Semiconductor is a high-integration connectivity processor combining a 96 MHz CR16CPlus RISC CPU with 4 KB instruction cache, a Teak® 16-bit fixed-point DSP coprocessor, integrated Bluetooth 1.2 Lower Link Controller (LLC), dual CAN 2.0B interfaces (up to 1 Mbps), USB 2.0 OTG controller, and audio/telematics codec - designed for embedded Bluetooth systems requiring simultaneous wireless, wired, and real-time audio processing.
For engineers reviewing the CP3SP33SMR/NOPB datasheet, CP3SP33SMR/NOPB pinout, CP3SP33SMR/NOPB application, or CP3SP33SMR/NOPB equivalent, key selection considerations include its FBGA-144 package with 36 I/O pins, dual CAN message buffer architecture (15 buffers per channel), Bluetooth sequencer RAM (1 KB) and data RAM (7 KB), and support for industrial temperature range (–40°C to +85°C).
Technical Context
The CP3SP33SMR/NOPB implements an AMBA-compliant AHB/APB bus architecture with independent CPU and DSP buses operating up to 96 MHz, enabling concurrent high-bandwidth operations: the CR16CPlus core handles protocol stack and system control while the Teak DSP offloads CVSD/PCM conversion, acoustic echo cancellation, and MP3/WMA decoding using dedicated 24 KB program RAM and 24 KB data RAM.
Its dual CAN modules operate in Full CAN 2.0B mode with memory-mapped 15-message buffers per channel, programmable transmit priority, automatic remote transmission request handling, and 16-bit timestamping - all accessible via CPU/DMA without software polling. The integrated Bluetooth LLC hardware accelerates baseband processing, reducing CPU load during piconet/scatternet operation and eSCO link management.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | CR16CPlus RISC, 0–96 MHz operation, 10.4 ns instruction cycle at 96 MHz - enables deterministic real-time control of Bluetooth host stack and peripheral drivers. |
| DSP Core | Teak 16-bit fixed-point, dual-MAC, 96 MHz max - supports concurrent CVSD/PCM conversion for two bidirectional audio paths and low-latency noise reduction. |
| Bluetooth Compliance | Hardware LLC compliant with Bluetooth Specification v1.2 - includes 7 KB dedicated data RAM and 1 KB sequencer RAM, enabling full packet handling and fast frequency hopping (1600 hops/s) without CPU intervention. |
| CAN Interfaces | Dual CAN 2.0B controllers, each with 15 configurable message buffers, 1 Mbps max rate, and hardware timestamping - suitable for automotive body control and industrial fieldbus nodes requiring deterministic message scheduling. |
| USB Interface | USB 2.0 On-The-Go node/host controller with integrated transceiver and 7 endpoint pipes - supports control, bulk, interrupt, and isochronous transfers without external PHY components. |
| Audio Codec | Integrated telematics/audio codec with dual 10-bit ADC (8–24 kHz sampling) and stereo DAC with click/pop suppression - eliminates need for external audio front-end in hands-free car kits and portable headsets. |
| Memory Resources | 32 KB CPU RAM, 4 KB shared CPU/DSP RAM, 24 KB DSP program RAM, 24 KB DSP data RAM, 8 KB Bluetooth RAM - provides sufficient on-chip storage for real-time OS, protocol stack, and audio buffers without external SRAM. |
| Package & I/O | FBGA-144 package with 36 multiplexed I/O pins - supports compact PCB layout for space-constrained Bluetooth modules while retaining access to UART, SPI, I²C, and GPIO functions. |
Pinout & Package
CP3SP33SMR/NOPB is housed in a 144-ball Fine-Pitch Ball Grid Array (FBGA-144) package with 0.8 mm ball pitch, designed for industrial temperature operation (–40°C to +85°C). Pin assignments are defined in National Semiconductor's CP3SP33 Datasheet Rev. 1.0 (September 2005), Section 5 "Pin Descriptions".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE | Core power supply | 1.8 V supply for CPU/DSP logic - requires low-noise regulation due to high-speed switching current demands. |
| VDD_IO | I/O power supply | 3.0–3.3 V supply for all digital I/O banks - supports mixed-voltage interfacing with USB, CAN transceivers, and external memory. |
| XTAL_IN / XTAL_OUT | Main clock oscillator interface | 12 MHz crystal connection for primary system clock generation - feeds PLLs for CPU, DSP, and audio subsystem clocks. |
| RTC_XTAL_IN / RTC_XTAL_OUT | Real-time clock oscillator interface | 32.768 kHz crystal input for low-power timing and watchdog - enables wake-up from Power Save/Idle modes without main oscillator activation. |
| CAN0_TX / CAN0_RX | Channel 0 CAN differential pair | Direct connection to external CAN transceiver (e.g., National's LM3S101) - supports high-speed (1 Mbps) or fault-tolerant low-speed CAN networks. |
| CAN1_TX / CAN1_RX | Channel 1 CAN differential pair | Independent second CAN interface - allows dual-bus architectures such as diagnostic + control bus in automotive ECUs. |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) USB signaling with integrated pull-up resistor on DP - eliminates external termination components for USB device enumeration. |
| BT_CLK / BT_DATA | BlueRF-compatible interface | Mode 2/3 serial interface to LMX5252/LMX5251 Bluetooth RF transceivers - enables direct hardware handshake for baseband-to-RF handoff. |
Key Features
| Feature | Design Value |
|---|---|
| Dual CAN with 15-message buffers per channel | Enables autonomous message filtering, prioritized transmission, and timestamped reception - reduces CPU overhead in real-time vehicle network applications. |
| Integrated Bluetooth LLC hardware accelerator | Offloads link-layer packet assembly/disassembly, CRC calculation, and frequency hop sequencing - frees >30% CPU bandwidth for application-layer tasks. |
| USB 2.0 OTG with embedded transceiver | Supports both device and host roles using single differential pair and internal pull-up - simplifies dual-role peripheral design (e.g., Bluetooth adapter that also hosts HID devices). |
| Teak DSP with 4 KB shared RAM | Allows zero-copy audio data exchange between CPU and DSP - critical for low-latency voice processing in hands-free telephony systems. |
| Multi-Input Wake-Up (MIWU) with 64 channels | Permits selective wake-up from Halt/Idle modes via CAN, UART, timer, or external GPIO events - extends battery life in portable Bluetooth gateways. |
| Audio/telematics codec with stereo DAC and dual ADC | Provides complete analog front-end for mono microphone input and stereo line output - eliminates need for external codec IC in cost-sensitive automotive infotainment modules. |
Applications
| Automotive Hands-Free Kit | Industrial CAN Gateway |
|---|---|
|
Use Scenario: In-vehicle Bluetooth hands-free system connecting mobile phones to vehicle audio via A2DP and HFP profiles. IC Role / Device Role / Timing Role: Central connectivity processor managing Bluetooth baseband, USB diagnostics, dual CAN bus bridging, and real-time audio codec processing. Use Value: Single-chip integration of Bluetooth LLC, dual CAN, USB OTG, and stereo DAC eliminates 4+ discrete ICs and reduces BOM cost by ~35% versus multi-chip solutions. |
Use Scenario: Protocol translation gateway between CAN-based sensor networks and USB-connected PC-based SCADA systems. IC Role / Device Role / Timing Role: Real-time bridge controller with deterministic CAN message buffering, USB bulk transfer scheduling, and timestamp synchronization across buses. Use Value: Hardware-accelerated CAN message filtering and USB isochronous support ensures sub-10 ms end-to-end latency for time-critical industrial monitoring data. |
| Portable Bluetooth Audio Adapter | Telematics Control Unit (TCU) |
|
Use Scenario: Compact USB-powered dongle converting Bluetooth A2DP streams to analog stereo output for legacy audio equipment. IC Role / Device Role / Timing Role: Standalone Bluetooth audio endpoint with integrated DAC, USB host interface, and power-managed sleep/wake control. Use Value: On-chip 10-bit ADC and stereo DAC eliminate external audio converters; USB self-powering enables plug-and-play operation without external power supply. |
Use Scenario: Vehicle-mounted TCU aggregating GPS, cellular modem, CAN bus data, and Bluetooth phone connectivity for fleet management. IC Role / Device Role / Timing Role: Primary application processor running RTOS, managing Bluetooth HFP/SDP, dual CAN diagnostics, and telematics codec I/O. Use Value: Shared 4 KB CPU/DSP RAM enables tight coupling between voice call handling (DSP) and modem command parsing (CPU), reducing inter-processor communication latency by 60%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar connectivity processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CP3SP33SMS/NOPB | Same core architecture but FBGA-224 package with 64 I/O pins - adds UART3, additional SPI, and full GPIO set not available in CP3SP33SMR/NOPB. | Suitable for designs requiring maximum peripheral expansion (e.g., multi-radio gateways with Bluetooth + Wi-Fi coexistence). | Select CP3SP33SMS/NOPB only if full 64-pin I/O capability and extra UART/SPI channels are required; CP3SP33SMR/NOPB suffices for cost-optimized 36-I/O implementations. |
| NXP LPC2478FBD208 | ARM7TDMI-based MCU with USB 2.0 OTG and CAN, but no integrated Bluetooth LLC, DSP, or audio codec - requires external Bluetooth module and audio ICs. | Better suited for general-purpose industrial control where Bluetooth is optional and added via external module. | Choose LPC2478FBD208 when flexibility in RF vendor selection and modular Bluetooth integration outweigh the BOM and layout complexity penalties of external components. |
Compared with CP3SP33SMS/NOPB, CP3SP33SMR/NOPB trades I/O count and peripheral density for smaller footprint and lower cost, while compared with LPC2478FBD208 it delivers higher integration of Bluetooth, audio, and dual CAN - reducing total component count by up to 7 parts in Bluetooth-centric telematics designs.
Availability
CP3SP33SMR/NOPB is available at Aetrix Electronics and suitable for automotive hands-free systems, industrial CAN gateways, portable Bluetooth audio adapters, and telematics control units requiring stable component supply across extended product lifecycles.
Supply support for CP3SP33SMR/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog and mixed-signal ICs, acquired by Texas Instruments in 2011. It pioneered highly integrated connectivity solutions for embedded wireless applications.
The CP3SP33 product line was developed to address the convergence of Bluetooth, CAN, USB, and real-time audio in automotive and industrial telematics - delivering single-chip system-on-a-chip capability before mainstream ARM-based alternatives existed.
FAQ
What is the maximum operating frequency of the CP3SP33SMR/NOPB CPU core?
The CP3SP33SMR/NOPB features a CR16CPlus RISC CPU core rated for operation up to 96 MHz, achieving a minimum instruction cycle time of 10.4 ns. This frequency is sustained using the 12 MHz external crystal input multiplied by internal PLLs, and the core remains fully functional across the industrial temperature range (–40°C to +85°C). The CP3SP33SMR/NOPB datasheet confirms this speed grade under all specified voltage and thermal conditions.
Does CP3SP33SMR/NOPB include hardware support for Bluetooth protocol stack acceleration?
Yes, CP3SP33SMR/NOPB integrates a dedicated Bluetooth Lower Link Controller (LLC) compliant with Bluetooth Specification v1.2, including 7 KB of Bluetooth data RAM and 1 KB of Bluetooth sequencer RAM. This hardware block handles packet assembly/disassembly, CRC computation, access code correlation, and slot timing recovery - significantly reducing CPU load during active Bluetooth links compared to software-only implementations.
How many CAN interfaces does CP3SP33SMR/NOPB support, and what is their compliance level?
CP3SP33SMR/NOPB supports two independent CAN interfaces, each conforming to CAN Specification 2.0B Active. Each channel provides 15 memory-mapped message buffers, programmable transmit priority, hardware timestamping, and diagnostic features including loopback and listen-only modes. Both CAN modules operate at rates up to 1 Mbps and support wake-up from low-power modes via the MIWU unit.
What audio capabilities are integrated into CP3SP33SMR/NOPB?
CP3SP33SMR/NOPB integrates a full telematics/audio codec with dual 10-bit ADC channels (8–24 kHz sampling), stereo DAC output with click/pop suppression, and support for differential or single-ended microphone inputs. It also includes two CVSD/PCM conversion modules compliant with Bluetooth audio encoding standards, enabling simultaneous bidirectional voice paths without external audio ICs.
Is CP3SP33SMR/NOPB pin-compatible with other members of the CP3SP33 family?
No, CP3SP33SMR/NOPB is not pin-compatible with CP3SP33SMS/NOPB: it uses the FBGA-144 package with 36 I/O pins, whereas CP3SP33SMS/NOPB uses FBGA-224 with 64 I/O pins and different ball mapping. While both share identical core functionality and register-level compatibility, PCB layout must be redesigned when migrating between these variants due to differing pin counts and physical footprints.
CP3SP33SMR/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 144-LFBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Connectivity Processor
- Core Processor:
- CR16C
- Program Memory Type:
- External Program Memory
- Controller Series:
- CP3000
- RAM Size:
- 44K x 8
- Interface:
- ACCESS.bus, Audio, Bluetooth, CAN, EBI/EMI, I2S, Microwire/SPI, UART/USART, USB OTG
- Number of I/O:
- 36
- Voltage - Supply:
- 3V ~ 3.3V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 144-FBGA (10x10)
CP3SP33SMR/NOPB FAQ
1.How can I place an order for CP3SP33SMR/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for CP3SP33SMR/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CP3SP33SMR/NOPB reliable?
The price and inventory of CP3SP33SMR/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CP3SP33SMR/NOPB is usually 5 days.
3.What payment methods are accepted for CP3SP33SMR/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CP3SP33SMR/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CP3SP33SMR/NOPB?
CP3SP33SMR/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CP3SP33SMR/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CP3SP33SMR/NOPB?
For technical support, including CP3SP33SMR/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CP3SP33SMR/NOPB requirements.
6.How does Aetrix verify that CP3SP33SMR/NOPB is sourced from the original manufacturer or authorized distributors?
All CP3SP33SMR/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CP3SP33SMR/NOPB meets industry standards.
7.What is the process for return or replacement of CP3SP33SMR/NOPB?
All CP3SP33SMR/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with CP3SP33SMR/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CP3SP33SMR/NOPB part is unused and in its original packaging.
Return procedure for CP3SP33SMR/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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