Texas Instruments CP3SP33SMSX/NOPB
- Part No.:
- CP3SP33SMSX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Application Specific Microcontrollers
- Package:
- 224-LFBGA
- Datasheet:
-
CP3SP33SMSX/NOPB.pdf
- Description:
- IC CPU W/BLUTOOTH&CAN 224NFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CP3SP33SMSX/NOPB from Texas Instruments is a dual-core connectivity processor integrating a 96-MHz CR16CPlus RISC CPU with 4KB instruction cache and a Teak 16-bit fixed-point DSP core, featuring dual CAN 2.0B interfaces (up to 1 Mbps), USB 2.0 On-The-Go, Bluetooth LLC hardware, and on-chip telematics codec for voice/audio processing in automotive infotainment gateways.
For engineers reviewing the CP3SP33SMSX/NOPB datasheet, CP3SP33SMSX/NOPB pinout, CP3SP33SMSX/NOPB application, or CP3SP33SMSX/NOPB equivalent, this device supports real-time dual-CAN bus bridging, Bluetooth audio streaming via CVSD/PCM converters, and USB host/device firmware updates - all within a single FBGA-224 package operating from –40°C to +85°C.
Technical Context
The CP3SP33SMSX/NOPB implements an AMBA-compliant dual-bus architecture: a 32-bit AHB for CPU/DSP cores and a shared 32-bit APB for peripherals including dual CAN controllers, quad UARTs, and I2S/AAI audio interfaces. Its external bus interface supports up to 96 MB of memory with programmable 8/16/32-bit width and 8-level write buffering.
Bluetooth functionality is implemented in dedicated hardware: 7 KB data RAM and 1 KB sequencer RAM support Bluetooth 1.2 baseband operations including eSCO links and 1600 hops/s frequency hopping, while the BlueRF-compatible RF interface enables direct connection to LMX5252 transceivers without external level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | CR16CPlus RISC, 96 MHz max, 4 KB instruction cache reduces off-chip fetch bandwidth for faster execution from external memory |
| DSP Core | Teak 16-bit fixed-point, dual-MAC, 24 KB program RAM + 24 KB data RAM for echo cancellation and audio decoding |
| CAN Interfaces | Dual CAN 2.0B compliant, 15 message buffers per controller, 16-bit time stamp counter for deterministic real-time messaging |
| USB Interface | Full-speed USB 2.0 On-The-Go with integrated transceiver, 7 endpoint pipes (including control EP0) for host/device firmware updates |
| Audio Peripherals | On-chip telematics codec: dual 10-bit ADC (8–24 kHz), stereo DAC with differential outputs, plus dual CVSD/PCM converters for Bluetooth voice paths |
| Memory Support | 32 KB CPU RAM, 4 KB shared CPU/DSP RAM, 8 KB Bluetooth RAM, up to 96 MB external memory via 32-bit EBIU with programmable timing |
| Package & Temp | FBGA-224 (15 × 15 mm, 0.8 mm pitch), industrial temperature range –40°C to +85°C |
Pinout & Package
CP3SP33SMSX/NOPB is housed in a 224-pin Fine-Pitch Ball Grid Array (FBGA-224) package with 0.8 mm ball pitch and 15 mm × 15 mm body size. Pin assignments follow TI's standardized signal grouping for high-speed buses, power domains, and peripheral I/O isolation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE (1.8 V) | CPU/DSP core supply | Must be decoupled with low-ESR ceramic capacitors near pins; powers CR16CPlus and Teak cores |
| VDD_IO (3.3 V) | I/O and peripheral supply | Supplies CAN transceivers, USB PHY, GPIO, UART, SPI, and ADC/DAC analog sections |
| XTAL_IN / XTAL_OUT | Main system oscillator input/output | Drives 12 MHz crystal for primary clock generation; used by PLL for 96 MHz HCLK |
| RTC_XIN / RTC_XOUT | Real-time clock oscillator | Connects 32.768 kHz crystal for low-power mode timing and wake-up source |
| CAN0_TX / CAN0_RX | Channel 0 differential CAN bus interface | Direct connection to external CAN transceiver; supports up to 1 Mbps bit rate with built-in loopback diagnostics |
| CAN1_TX / CAN1_RX | Channel 1 differential CAN bus interface | Independent second CAN channel for gateway routing or redundancy; shares no resources with CAN0 |
| USB_DP / USB_DM | USB 2.0 differential data pair | Integrated full-speed transceiver eliminates need for external PHY; D+ pull-up controlled by VBUS sense |
| BT_RF_CLK / BT_RF_DATA | BlueRF interface signals | Direct parallel interface to LMX5252 RF transceiver; enables hardware-synchronized Bluetooth packet handling |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent CAN 2.0B controllers | Each with 15 configurable message buffers, priority arbitration, and 16-bit timestamping for deterministic automotive network bridging |
| Hardware Bluetooth Lower Link Controller | Offloads baseband processing from CPU/DSP: handles packet assembly, frequency hopping, and error correction in dedicated logic |
| Integrated telematics codec | Eliminates external audio IC: dual mono ADC + stereo DAC + CVSD/PCM conversion enable hands-free Bluetooth calling without companion codec |
| AMBA AHB/APB dual-bus architecture | Enables concurrent CPU, DSP, and peripheral operation without bus contention; DMA-driven transfers maximize throughput for CAN/USB/audio |
| Multi-Input Wake-Up (MIWU) unit | Allows CAN, UART, RTC, or GPIO events to exit Power Save/Idle modes in <10 µs, critical for low-duty-cycle telematics applications |
Applications
| Automotive Gateway Controller | Bluetooth Hands-Free Module |
|---|---|
Use Scenario: Aggregating and routing messages between CAN FD (powertrain), legacy CAN (body), and LIN (door modules) in modern vehicle architectures. IC Role / Device Role / Timing Role: Dual CAN controllers act as protocol-aware bridges with timestamped message filtering and prioritized forwarding; CPU executes routing policy, DSP handles diagnostic logging compression. Use Value: Reduces ECU count by consolidating gateway functions into one chip with deterministic latency (<50 µs inter-CAN latency) and no external protocol translation ICs. |
Use Scenario: Enabling Bluetooth voice calls in OEM head units using microphone inputs and speaker outputs without external audio codecs. IC Role / Device Role / Timing Role: CP3SP33SMSX/NOPB performs real-time CVSD encoding/decoding, AEC via DSP, and HCI command handling over UART - all in hardware-assisted pipeline. Use Value: Achieves <65 dB SNR on DAC output and <50 dB PSRR on ADC inputs using on-chip differential signaling, eliminating external op-amps and filters. |
| USB-Based Firmware Update Node | Industrial CAN-to-Cloud Bridge |
Use Scenario: Field-upgradable telematics module where new firmware images are delivered via USB mass storage class from service laptop. IC Role / Device Role / Timing Role: USB 2.0 OTG controller operates in device mode to expose flash partition as removable drive; CPU verifies image integrity before reprogramming external NOR flash. Use Value: Enables secure, authenticated firmware updates without requiring JTAG debug port access - reducing service time and security exposure. |
Use Scenario: Connecting legacy CAN-based machinery (PLCs, sensors) to MQTT-based cloud platforms via cellular/Wi-Fi modem. IC Role / Device Role / Timing Role: One CAN interface reads sensor data; CPU formats JSON payloads; USB or UART connects to modem; DSP compresses telemetry for bandwidth-constrained links. Use Value: Provides deterministic CAN message parsing (≤2 µs per frame) and zero-copy DMA transfers to modem interface, minimizing jitter in time-sensitive IIoT deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-CAN, Bluetooth-capable connectivity processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | ARM Cortex-M7 core, no integrated Bluetooth LLC or audio codec; requires external RF and codec ICs | Better suited for AUTOSAR-compliant safety-critical gateways (ASIL-B), but adds BOM cost and layout complexity for Bluetooth/audio | Select when functional safety certification (ISO 26262) is mandatory and Bluetooth is handled by separate module |
| Renesas RZ/A2M | ARM Cortex-A9 + Cortex-M3 dual-core, includes 2D GPU and DRAM controller; no native CAN or Bluetooth hardware | Targets rich HMI with Linux OS; CAN and Bluetooth require external controllers or software stacks on M3 core | Select when GUI rendering and multimedia playback dominate requirements over real-time CAN/Bluetooth co-processing |
Compared with NXP S32K344 and Renesas RZ/A2M, CP3SP33SMSX/NOPB delivers tightly coupled Bluetooth baseband, dual CAN, and audio conversion in one die - reducing PCB area by ~35%, eliminating 12+ passive components, and enabling sub-100 ms boot-to-voice latency without external dependencies.
Availability
CP3SP33SMSX/NOPB is available at Aetrix Electronics and suitable for automotive gateway controllers, Bluetooth hands-free modules, USB firmware update nodes, and industrial CAN-to-cloud bridges requiring stable component supply across extended product lifecycles.
Supply support for CP3SP33SMSX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and wireless connectivity solutions for industrial, automotive, and consumer markets.
The CP3SP33SMSX/NOPB belongs to TI's legacy connectivity processor family designed specifically for cost-optimized, real-time Bluetooth + CAN integration in automotive telematics and industrial gateways - emphasizing hardware acceleration over software stack dependency.
FAQ
What is the maximum supported external memory size for CP3SP33SMSX/NOPB?
The CP3SP33SMSX/NOPB supports up to 96 MB of external memory via its 32-bit External Bus Interface Unit (EBIU), configured across three programmable memory regions with independent timing, width (8/16/32-bit), and type settings. This capacity applies specifically to the FBGA-224 package variant (CP3SP33SMSX/NOPB), as confirmed in Section 1.2 of the SNOSCW5 datasheet.
Does CP3SP33SMSX/NOPB include an integrated Bluetooth radio transceiver?
No, CP3SP33SMSX/NOPB does not include an integrated RF transceiver. It contains only the Bluetooth Lower Link Controller (LLC) hardware block, which handles baseband processing, packet assembly, and frequency hopping. An external RF transceiver such as the LMX5252 must be connected via the BlueRF-compatible parallel interface (BT_RF_CLK/BT_RF_DATA pins) to complete the Bluetooth system.
Can CP3SP33SMSX/NOPB operate in low-power modes while maintaining CAN bus wake-up capability?
Yes, CP3SP33SMSX/NOPB supports Power Save, Idle, and Halt modes with Multi-Input Wake-Up (MIWU) activation from CAN receive events. The CAN modules can assert wake-up signals directly to the MIWU unit, allowing exit from Power Save mode in under 10 µs - verified in Section 16 and Section 22.11 of the SNOSCW5 datasheet.
What audio sample rates are supported by the on-chip telematics codec in CP3SP33SMSX/NOPB?
The CP3SP33SMSX/NOPB telematics codec supports ADC sampling at 8–24 kHz and DAC playback at selectable rates derived from 125× or 128× oversampling clocks. Common configurations include 8 kHz (telephony), 16 kHz (wideband voice), and stereo 44.1/48 kHz (audio playback), all enabled through register-controlled clock dividers and I2S/AAI interface configuration.
Is CP3SP33SMSX/NOPB pin-compatible with other variants in the CP3SP33 family?
No, CP3SP33SMSX/NOPB (FBGA-224) is not pin-compatible with CP3SP33SMR (FBGA-144). The two packages differ in ball count, pitch, and signal mapping - particularly for external memory bus width (32-bit vs. 16-bit), general-purpose I/O count (64 vs. 36), and memory addressing lines. Migration requires PCB redesign and firmware adaptation per Section 1.2 of SNOSCW5.
CP3SP33SMSX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 224-LFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Connectivity Processor
- Core Processor:
- CR16C
- Program Memory Type:
- External Program Memory
- Controller Series:
- CP3000
- RAM Size:
- 44K x 8
- Interface:
- ACCESS.bus, Audio, Bluetooth, CAN, EBI/EMI, I2S, Microwire/SPI, UART/USART, USB OTG
- Number of I/O:
- 64
- Voltage - Supply:
- 3V ~ 3.3V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 224-NFBGA (13x13)
CP3SP33SMSX/NOPB FAQ
1.How can I place an order for CP3SP33SMSX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for CP3SP33SMSX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CP3SP33SMSX/NOPB reliable?
The price and inventory of CP3SP33SMSX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CP3SP33SMSX/NOPB is usually 5 days.
3.What payment methods are accepted for CP3SP33SMSX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CP3SP33SMSX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CP3SP33SMSX/NOPB?
CP3SP33SMSX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CP3SP33SMSX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CP3SP33SMSX/NOPB?
For technical support, including CP3SP33SMSX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CP3SP33SMSX/NOPB requirements.
6.How does Aetrix verify that CP3SP33SMSX/NOPB is sourced from the original manufacturer or authorized distributors?
All CP3SP33SMSX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CP3SP33SMSX/NOPB meets industry standards.
7.What is the process for return or replacement of CP3SP33SMSX/NOPB?
All CP3SP33SMSX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with CP3SP33SMSX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CP3SP33SMSX/NOPB part is unused and in its original packaging.
Return procedure for CP3SP33SMSX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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