Renesas DA9063-00HO1
- Part No.:
- DA9063-00HO1
- Manufacturer:
- Renesas
- Category:
- Power Management - Specialized
- Package:
- 100-TFBGA
- Datasheet:
-
DA9063-00HO1.pdf
- Description:
- 14.2A SYSTEM PMIC (6 BUCKS + 11
- Quantity:
- Payment:

- Shipping:

Inventory:3,868
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Product details
Overview
DA9063-00HO1 from Renesas Electronics is a high-current system PMIC designed for dual- and quad-core processors in smartphones, tablets, ultrabooks, and automotive infotainment systems. It integrates six DC-DC buck converters (up to 2.5 A each), eleven programmable LDOs (up to 300 mA), a 10-bit 10-channel ADC, RGB-LED drivers, and PWM-controlled vibration motor driver - all operating from a single VSYS input up to 5.5 V.
For engineers reviewing the DA9063-00HO1 datasheet, DA9063-00HO1 pinout, DA9063-00HO1 application, or DA9063-00HO1 equivalent, key selection considerations include its dual-phase 5 A core supply capability, AEC-Q100 Grade 2 qualification (for automotive variants), OTP-programmable power sequencing, and support for DDR memory termination mode on BUCKPRO.
Technical Context
The DA9063-00HO1 implements a hardware-based OTP start-up sequencer with configurable slot delays and autonomous power-up/down control, enabling deterministic boot without host processor intervention. Its six buck converters operate at 3 MHz (±10 %) with automatic sleep mode and dynamic voltage control (DVC) across four LDOs and three bucks, supporting real-time processor load adaptation.
It features two independent control interfaces - a high-speed 2-wire bus (HS-2-Wire) and a standard 4-wire/2-wire bus - allowing concurrent master access. The integrated 10-bit ADC supports manual and auto-scheduled conversions with programmable thresholds for nine channels including temperature, battery voltage, and external resistive sensors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | Up to 2.5 A per buck (BUCKCORE1/2/PRO); merged mode enables 3 A on BUCKMEM/IO or 5 A dual-phase on CORE rails. |
| Switching Frequency | 3 MHz ±10 % - enables use of compact 1 µH, 1 mm height inductors and reduces output capacitance requirements. |
| LDO Count & Rating | 11 SmartMirror™ LDOs; 3 low-noise, 4 DVC-capable, 5 with current-limited switch mode; max 300 mA per LDO. |
| ADC Resolution & Channels | 10-bit resolution in manual mode, 8-bit in AUTO mode; 10-channel input mux with 3 general-purpose, 3 thermal/voltage supervision, and 4 dedicated monitoring inputs. |
| RTC Power Consumption | 1.5 µA in RTC mode with alarm and wake-up - enables always-on timekeeping with minimal battery drain. |
| Operating Temperature | –40 °C to +125 °C junction temperature - qualified for automotive Grade 2 applications when configured as DA9063-A variant. |
| Control Interfaces | Dual-interface support: HS-2-Wire (up to 10 MHz) and standard 4-wire/2-wire bus - allows simultaneous host and peripheral control. |
Pinout & Package
DA9063-00HO1 is packaged in a 100-ball VFBGA (8.0 mm × 8.0 mm × 1.0 mm, 0.8 mm pitch, 0.30 mm solder balls), optimized for high-density mobile and automotive PCB layouts with dedicated quiet/noisy ground planes and high-power signal routing zones.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply input | Accepts regulated 0.3–3.3 V input for internal logic; decoupled via 2.2 µF capacitor to minimize noise coupling into digital core. |
| SWBUCKCORE1_A/B | High-side switch node | Connects directly to external 1 µH inductor; requires low-inductance layout to minimize switching losses and EMI in dual-phase operation. |
| GPIO0–GPIO15 | Configurable I/O | 16 pins support keypad scan, wake-up event detection, external regulator enable, or PWM output - programmable pull-up/down and interrupt capability. |
| nIRQ | Interrupt request output | Open-drain active-low signal indicating regulator fault, ADC threshold breach, thermal warning, or RTC alarm - drives host processor interrupt line. |
| XTAL_IN / XTAL_OUT | 32 kHz crystal interface | Supports external tuning capacitor (12 pF typical) for ±100 ppm frequency accuracy; enables crystal oscillator calibration via OTP registers. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-phase buck architecture | Enables 5 A core supply using two parallel 2.5 A BUCKCORE rails - reduces thermal stress and improves transient response vs. single-rail solutions. |
| OTP-programmable sequencing | Hardware-based start-up sequence stored in one-time-programmable memory - eliminates dependency on host firmware for safe, repeatable power-up timing. |
| DDR memory termination mode | BUCKPRO reconfigures as a 0.75 V, ±1% precision termination supply - replaces discrete termination ICs and simplifies DDR3/4 memory interface design. |
| PWM vibration motor driver | LDO8 operates as 6-bit PWM-controlled driver with automatic battery voltage compensation - eliminates need for external H-bridge and feedback circuitry. |
| Ultra-low-power RTC mode | 1.5 µA quiescent current with full calendar, alarm, and 32 kHz oscillator - extends coin-cell or supercapacitor backup runtime beyond 1 year. |
Applications
| Smartphone Power Management | Automotive Infotainment System |
|---|---|
Use Scenario: Dual-core application processor (e.g., ARM Cortex-A53/A72) with multi-rail voltage requirements and thermal constraints in slim form factor. IC Role / Device Role / Timing Role: Central system PMIC providing dynamically scaled core, GPU, memory, and I/O supplies with hardware-sequenced boot and real-time DVC. Use Value: Reduces BOM count by integrating 6 bucks + 11 LDOs + ADC + RTC + LED/motor drivers - cuts PCB area by >40% vs. discrete solution. | Use Scenario: Head-unit display controller requiring AEC-Q100 compliance, extended temperature operation, and fail-safe power sequencing. IC Role / Device Role / Timing Role: Automotive-grade power manager delivering isolated domain control, rail fault detection, watchdog supervision, and cold-crank tolerant startup. Use Value: Meets ASIL-B functional safety prerequisites via hardware watchdog, under/over-voltage protection, and redundant power enable signaling. |
| Tablet DDR Memory Interface | Industrial Portable HMI |
Use Scenario: High-resolution tablet SoC with LPDDR4 memory requiring precise VTT termination and dynamic VDDQ scaling. IC Role / Device Role / Timing Role: BUCKPRO configured in DDR termination mode; BUCKMEM/IO supply VDDQ and VTT with synchronized DVC tracking. Use Value: Eliminates external termination IC and discrete VTT regulators - improves signal integrity and reduces layout complexity for high-speed memory buses. | Use Scenario: Ruggedized handheld HMI with touchscreen, RGB status LEDs, haptic feedback, and long-life battery operation. IC Role / Device Role / Timing Role: Single-chip power + sensing + actuation hub managing display backlight, touch controller supply, LED indicators, and vibration motor drive. Use Value: Integrates RGB-LED PWM dimming, 6-bit haptic control, and 10-bit ADC for battery voltage/temperature monitoring - removes 5+ discrete components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar system PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX77818EWL+T | 5-buck + 10-LDO architecture; 2.2 MHz switching; no DDR termination mode; lacks integrated vibration motor driver. | Targeted at Android smartphones only; not AEC-Q100 qualified; no RTC backup charging. | Preferred where cost-sensitive consumer designs require proven Android compatibility but lack automotive or haptic requirements. |
| TPS659122ZQV | 6-buck + 11-LDO; 2.5 MHz switching; includes USB OTG boost; no OTP sequencer; uses software-controlled sequencing only. | Designed for TI Sitara AMx processors; limited GPIO flexibility; no RGB-LED or vibration motor integration. | Best suited for TI ecosystem designs needing USB power delivery but accepting firmware-dependent sequencing and reduced peripheral integration. |
Compared with MAX77818EWL+T and TPS659122ZQV, DA9063-00HO1 uniquely combines AEC-Q100 readiness, hardware OTP sequencing, DDR termination capability, and integrated haptic/RGB drive - reducing system-level validation effort and component count in mixed-domain (mobile + automotive) platforms.
Availability
DA9063-00HO1 is available at Aetrix Electronics and suitable for smartphone power management, automotive infotainment systems, tablet DDR memory interfaces, and industrial portable HMI applications requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for DA9063-00HO1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog power, and SoC solutions for automotive, industrial, and IoT markets - with deep expertise in power management architecture and functional safety certification.
The DA9063-00HO1 belongs to Renesas' System PMIC product line, engineered specifically for heterogeneous processor platforms requiring tightly coordinated multi-rail power delivery, autonomous sequencing, and integrated system monitoring in space-constrained, thermally demanding environments.
FAQ
What is the maximum continuous output current supported by DA9063-00HO1 for processor core rails?
DA9063-00HO1 supports up to 5 A continuous core supply using dual-phase operation across BUCKCORE1 and BUCKCORE2 - each rated at 2.5 A, with synchronized 3 MHz switching and shared inductor current sensing. This configuration is explicitly validated in the datasheet for high-performance mobile and automotive SoCs requiring stable, low-noise core voltage under dynamic load.
Does DA9063-00HO1 support DDR memory bus termination, and if so, which buck converter provides it?
Yes, DA9063-00HO1 supports DDR memory bus termination via BUCKPRO, which can be reconfigured in hardware or software to deliver a precise 0.75 V ±1% termination voltage with fast transient response. This mode is documented in Section 6.10.3 of the datasheet and eliminates the need for external termination ICs in LPDDR3/LPDDR4 designs.
Can DA9063-00HO1 operate in automotive environments, and what qualification does it meet?
DA9063-00HO1 itself is not AEC-Q100 qualified; however, the pin-compatible DA9063-A variant (same package and register map) is certified to AEC-Q100 Grade 2 (–40 °C to +105 °C ambient). DA9063-00HO1 shares identical electrical characteristics and thermal design - making it suitable for pre-validation or non-safety-critical automotive subsystems where full qualification is pending.
How many GPIO pins does DA9063-00HO1 provide, and what are their key configurable functions?
DA9063-00HO1 provides 16 fully configurable GPIO pins (GPIO0–GPIO15), each supporting multiple roles including keypad scanning, external regulator enable, wake-up event detection, PWM output, and general-purpose digital I/O. All pins feature programmable pull-up/down, interrupt generation, and level-shifting capability between VDD_IO1/VDD_IO2 domains - enabling flexible system-level control without additional logic.
What is the resolution and channel count of the integrated ADC in DA9063-00HO1, and how is it used for system monitoring?
DA9063-00HO1 integrates a 10-bit general-purpose ADC with 10 input channels - including 3 general-purpose, 3 thermal/voltage supervision, and 4 dedicated monitoring inputs (e.g., battery voltage, VREF, temperature sensor). It operates in manual or auto-scheduled mode with programmable high/low thresholds, enabling real-time battery health monitoring, thermal throttling, and fault detection without host CPU intervention.
DA9063-00HO1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 100-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Processor
- Current - Supply:
- 11mA
- Voltage - Supply:
- 0V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TFBGA (8x8)
DA9063-00HO1 FAQ
1.How can I place an order for DA9063-00HO1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DA9063-00HO1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA9063-00HO1 reliable?
The price and inventory of DA9063-00HO1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9063-00HO1 is usually 5 days.
3.What payment methods are accepted for DA9063-00HO1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9063-00HO1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA9063-00HO1?
DA9063-00HO1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA9063-00HO1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA9063-00HO1?
For technical support, including DA9063-00HO1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9063-00HO1 requirements.
6.How does Aetrix verify that DA9063-00HO1 is sourced from the original manufacturer or authorized distributors?
All DA9063-00HO1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9063-00HO1 meets industry standards.
7.What is the process for return or replacement of DA9063-00HO1?
All DA9063-00HO1 units undergo pre-shipment inspection (PSI). If there is an issue with DA9063-00HO1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA9063-00HO1 part is unused and in its original packaging.
Return procedure for DA9063-00HO1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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