Renesas DA9063-A0HO2
- Part No.:
- DA9063-A0HO2
- Manufacturer:
- Renesas
- Category:
- Power Management - Specialized
- Package:
- 100-TFBGA
- Datasheet:
-
DA9063-A0HO2.pdf
- Description:
- 14.2A SYSTEM PMIC (6 BUCKS + 11
- Quantity:
- Payment:

- Shipping:

Inventory:3,538
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Product details
Overview
DA9063-A0HO2 from Renesas Electronics is a high-current system PMIC designed for dual- and quad-core processors in mobile and automotive applications, delivering up to 5 A core supply, integrating six DC-DC buck converters (total 12 A continuous), eleven programmable LDOs (up to 300 mA), and a 10-bit ADC with nine channels - used in car infotainment, ADAS, and ultra-books.
For engineers reviewing the DA9063-A0HO2 datasheet, DA9063-A0HO2 pinout, DA9063-A0HO2 application, or DA9063-A0HO2 equivalent, key selection considerations include its AEC-Q100 Grade 2 qualification, dual-phase 5 A core supply capability, OTP-programmable power sequencing, and support for DDR memory termination mode on BUCKPRO.
Technical Context
The DA9063-A0HO2 implements a hardware-based OTP start-up sequencer enabling autonomous system boot without host intervention, and supports two independent control interfaces: HS-2-WIRE (I²C-compatible) and 4-WIRE (SPI-like) for flexible host integration. Its power manager handles five ultra-low-power modes (<20 µA), including a 1.5 µA RTC mode with alarm and crystal frequency adjustment.
Buck regulation uses fixed 3 MHz switching (±10%) to enable compact 1 µH inductors; DVC is implemented on four LDOs and three bucks (BUCKCORE1/2, BUCKPRO) for dynamic processor voltage scaling. The integrated rail switch controller provides fast domain isolation with current-limited external peripheral switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Supply Capability | 5 A in dual-phase mode (BUCKCORE1 + BUCKCORE2), enabling high-efficiency CPU core powering for ARM Cortex-A series SoCs |
| Switching Frequency | 3 MHz ±10% - allows use of low-profile (1 mm height) 1 µH inductors, reducing board area and height |
| LDO Count & Rating | 11 SmartMirror™ LDOs, each up to 300 mA, with remote capacitor placement support and 1.5 V/1.8 V input compatibility |
| ADC Resolution & Channels | 10-bit resolution in manual mode, 8-bit in AUTO mode; 10-channel GPADC with programmable thresholds and internal current source for resistive sensing |
| Operating Temperature | −40 °C to +125 °C junction temperature - qualified per AEC-Q100 Grade 2 for automotive under-hood and infotainment use |
| RTC Current Draw | 1.5 µA in RTC mode - enables long-term real-time clock operation from coin cell or supercapacitor backup |
| Package Type | 100-ball VFBGA, 8.0 mm × 8.0 mm × 1.0 mm, 0.8 mm pitch, 0.30 mm solder balls - optimized for high-density mobile PCB layouts |
Pinout & Package
DA9063-A0HO2 is housed in a 100-ball Very Fine Pitch Ball Grid Array (VFBGA) package measuring 8.0 mm × 8.0 mm × 1.0 mm with 0.8 mm ball pitch and 0.30 mm solder spheres. This variant is designated A0HO2 per Renesas ordering nomenclature and corresponds to the automotive-grade AEC-Q100 Grade 2 version in VFBGA form factor.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core Power Input | Supplies internal logic and core regulator circuitry; requires local 2.2 µF ceramic decoupling |
| SWBUCKCORE1_A / SWBUCKCORE1_B | Buck Core1 Switch Node | Dual-phase output terminals for BUCKCORE1; must connect to same inductor in merged mode or separate inductors in dual-phase |
| nONKEY | Hardware On/Off Input | Active-low button detection pin with configurable long-press lockout and shutdown timing |
| nIRQ | Interrupt Request Output | Open-drain signal indicating regulator fault, ADC threshold breach, thermal warning, or RTC alarm |
| GP_FB1 / GP_FB2 / GP_FB3 | General-Purpose Feedback Signals | Configurable as outputs (e.g., PWR_OK, KEEP_ACT, OUT32K_2) or inputs (e.g., EXT_WAKEUP, nVIB_BRAKE) |
| ADCIN1 / ADCIN2 / ADCIN3 | Analog Inputs | Three dedicated ADC channels supporting voltage monitoring, temperature sensing, or resistive divider measurements |
| XTAL_IN / XTAL_OUT | 32 kHz Crystal Interface | Connects to external tuning fork crystal for RTC oscillator; supports ±100 ppm frequency trim via OTP registers |
Key Features
| Feature | Design Value |
|---|---|
| OTP Programmable Sequencing Engine | Enables hardware-autonomous power-up/down sequencing without host CPU involvement - critical for fail-safe automotive boot |
| Dual-Phase Core Buck Architecture | BUCKCORE1 and BUCKCORE2 operate in interleaved 180° phase to halve input/output ripple current and reduce EMI filtering requirements |
| DDR Memory Bus Termination Mode | BUCKPRO can be configured as a programmable 0.6–1.2 V termination supply with fast transient response for LPDDR3/LPDDR4 interfaces |
| PWM Vibration Motor Driver (LDO8) | 6-bit PWM-controlled LDO8 delivers regulated current to vibration motors with automatic battery voltage compensation to maintain consistent actuator intensity |
| Ultra-Low-Power RTC with Alarm | 1.5 µA RTC mode retains calendar/alarm functionality while disabling all other regulators - extends backup runtime from coin cell beyond 1 year |
| Two Independent Control Interfaces | HS-2-WIRE (I²C-compatible at up to 3.4 Mbps) and 4-WIRE (SPI-like) allow coexistence with multiple masters or legacy host controllers |
Applications
| Automotive Infotainment Head Unit | ADAS Camera Module Power System |
|---|---|
Use Scenario: Central display unit requiring simultaneous power to quad-core application processor, GPU, DDR memory, touchscreen controller, and audio codec. IC Role / Device Role / Timing Role: System PMIC providing coordinated, OTP-programmed power sequencing, dynamic core voltage scaling (DVC), and DDR termination supply. Use Value: Eliminates need for discrete power rails and sequencer ICs; reduces BOM count by 7+ components while meeting AEC-Q100 Grade 2 reliability requirements. |
Use Scenario: Compact rear-view or surround-view camera module operating in engine bay with wide temperature range and strict EMI limits. IC Role / Device Role / Timing Role: Primary power manager delivering isolated 1.1 V core, 1.8 V I/O, 3.3 V sensor bias, and 0.9 V DDR termination with fast wake-from-standby. Use Value: Dual-phase 5 A core supply ensures stable SoC operation during burst image processing; 3 MHz switching minimizes conducted EMI into analog video paths. |
| Industrial Tablet with LTE Modem | Connected Navigation Device |
Use Scenario: Ruggedized tablet used in logistics with LTE, GPS, barcode scanner, and extended battery life requirements. IC Role / Device Role / Timing Role: Central PMIC managing battery-to-rail conversion, modem sleep/wake coordination, and peripheral power gating via 16 GPIOs. Use Value: 11 LDOs with remote capacitor support enable clean analog supplies for RF front-end and GNSS receiver; RTC alarm wakes device on schedule without host CPU. |
Use Scenario: In-dash navigation system requiring always-on GPS tracking, map rendering, and voice guidance with minimal standby drain. IC Role / Device Role / Timing Role: Power supervisor providing 1.5 µA RTC mode, coin-cell backup charging, and programmable low-voltage warnings for battery health monitoring. Use Value: Backup charger maintains RTC accuracy during vehicle ignition-off periods; 10-bit ADC monitors battery voltage and internal die temperature for predictive shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar system PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX20029ATJ+T | 4-channel buck + 8 LDOs; no OTP sequencer; 2.2 MHz switching; AEC-Q100 Grade 2; lacks DDR termination mode and vibration motor driver | Targeted at simpler automotive body electronics (e.g., HVAC control), not compute-intensive infotainment or ADAS | Choose when full 6-buck + 11-LDO complexity and autonomous sequencing are unnecessary |
| TPS659122ZQV | 6 buck + 10 LDOs; 2.2 MHz switching; no AEC-Q100 qualification; supports only software-controlled sequencing via I²C | Suitable for consumer tablets and handhelds, but not certified for automotive deployment | Prefer for cost-sensitive non-automotive designs where AEC-Q100 compliance and hardware sequencer are not required |
Compared with MAX20029ATJ+T and TPS659122ZQV, DA9063-A0HO2 uniquely combines AEC-Q100 Grade 2 certification, OTP-based autonomous power sequencing, dual-phase 5 A core supply, and integrated DDR termination - making it the only option qualified for safety-critical automotive compute platforms requiring zero-host-boot dependency.
Availability
DA9063-A0HO2 is available at Aetrix Electronics and suitable for automotive infotainment, ADAS camera modules, and industrial tablets requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant power management.
Supply support for DA9063-A0HO2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The DA9063-A0HO2 belongs to Renesas' System PMIC product line, engineered specifically for high-reliability mobile and automotive computing platforms requiring integrated power sequencing, multi-rail efficiency, and functional safety-aware design.
FAQ
What is the AEC-Q100 qualification status of DA9063-A0HO2?
The DA9063-A0HO2 is fully qualified to AEC-Q100 Grade 2 (−40 °C to +105 °C ambient / −40 °C to +125 °C junction), with test reports covering HTOL, TC, UHAST, ESD, and AC/DC stress. This qualification applies specifically to the A0HO2 variant and confirms suitability for automotive infotainment and ADAS applications outside the engine compartment.
Does DA9063-A0HO2 support hardware-only power sequencing without host processor involvement?
Yes, DA9063-A0HO2 integrates an OTP-programmable power sequencer that executes autonomous start-up and shut-down sequences directly from on-chip memory. This eliminates dependency on host firmware during cold boot or reset recovery - a critical feature for automotive systems requiring deterministic power behavior.
Can DA9063-A0HO2 supply DDR memory termination voltage, and which buck channel provides it?
Yes, DA9063-A0HO2 supports DDR memory bus termination mode on BUCKPRO, configurable via register settings to deliver a precise, low-noise 0.6 V to 1.2 V output with fast transient response - validated for LPDDR3 and LPDDR4 interfaces in automotive head units.
How many GPIOs does DA9063-A0HO2 offer, and what are their key configurable functions?
DA9063-A0HO2 provides up to 16 freely configurable GPIO pins supporting keypad supervision, application wake-up, timing-controlled enable signals for external regulators or power switches, and general-purpose digital I/O - all programmable via I²C or SPI interface with interrupt capability.
What is the minimum supply current of DA9063-A0HO2 in RTC-only mode, and how is backup maintained?
DA9063-A0HO2 draws just 1.5 µA in RTC mode, enabling multi-year operation from a CR2032 coin cell. It includes an integrated backup battery charger that conditions and regulates charge current to the backup rail (VBBAT), supporting both coin cells and supercapacitors with programmable charge termination.
DA9063-A0HO2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 100-TFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Smart Phones
- Current - Supply:
- 320µA
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TFBGA (8x8)
DA9063-A0HO2 FAQ
1.How can I place an order for DA9063-A0HO2 through Aetrix?
Please submit a Request for Quotation (RFQ) for DA9063-A0HO2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA9063-A0HO2 reliable?
The price and inventory of DA9063-A0HO2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9063-A0HO2 is usually 5 days.
3.What payment methods are accepted for DA9063-A0HO2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9063-A0HO2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA9063-A0HO2?
DA9063-A0HO2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA9063-A0HO2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA9063-A0HO2?
For technical support, including DA9063-A0HO2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9063-A0HO2 requirements.
6.How does Aetrix verify that DA9063-A0HO2 is sourced from the original manufacturer or authorized distributors?
All DA9063-A0HO2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9063-A0HO2 meets industry standards.
7.What is the process for return or replacement of DA9063-A0HO2?
All DA9063-A0HO2 units undergo pre-shipment inspection (PSI). If there is an issue with DA9063-A0HO2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA9063-A0HO2 part is unused and in its original packaging.
Return procedure for DA9063-A0HO2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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