Renesas DA9063L-XXHO1-AT
- Part No.:
- DA9063L-XXHO1-AT
- Manufacturer:
- Renesas
- Category:
- Power Management - Specialized
- Package:
- 100-TFBGA
- Datasheet:
-
DA9063L-XXHO1-AT.pdf
- Description:
- ONCE OTP IS FINALIZED, PART BECO
- Quantity:
- Payment:

- Shipping:

Inventory:3,016
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DA9063L-XXHO1-AT from Renesas Electronics is a high-current system PMIC designed for dual- and quad-core application processors in mobile and automotive systems, delivering up to 5 A core supply, integrating six DC-DC buck converters (0.3–3.34 V, up to 2.5 A each), five SmartMirror™ LDOs (up to 300 mA), a 10-bit 9-channel ADC, RGB-LED/PWM vibration motor drivers, and programmable power sequencing. It supports DDR VTT termination, DVC, and AEC-Q100 Grade 2 compliance.
For engineers reviewing the DA9063L-XXHO1-AT datasheet, DA9063L-XXHO1-AT pinout, DA9063L-XXHO1-AT application, or DA9063L-XXHO1-AT equivalent, this device is selected for processor-centric power management requiring autonomous start-up, multi-rail voltage control, thermal supervision, I²C-configurable regulation, and low-quiescent operating modes (<20 µA) in space-constrained handheld and infotainment designs.
Technical Context
The DA9063L-XXHO1-AT implements a hardware-based OTP-programmable power sequencer with configurable slot delays and autonomous NO-POWER mode wake-up via nONKEY or CHG_WAKE. Its six buck converters operate at 3 MHz, enabling use of compact 1 µH inductors, and support dual-phase (BUCKCORE1/2 → 5 A), merged (BUCKMEM/IO), and DDR termination modes.
Five LDOs include one low-noise variant (LDO3), one DVC-capable regulator (LDO7), and four with current-limited switch options; all accept 1.5–1.8 V input for cascaded efficiency. The integrated 10-bit ADC monitors system voltage, junction temperature, and three general-purpose analog inputs with programmable thresholds and resistive sensing capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion and USB-powered systems without external pre-regulation. |
| Buck Output Range | 0.3 V to 3.34 V - covers core, memory, I/O, and peripheral rail requirements for modern APs and FPGAs. |
| Max Buck Current | 2.5 A per buck; dual-phase BUCKCORE1/2 delivers up to 5 A - enables high-performance CPU/GPU core supply with dynamic voltage scaling. |
| LDO Output Range | 0.9 V to 3.6 V, up to 300 mA - supports low-noise analog, sensor, and interface rails with remote capacitor placement. |
| ADC Resolution & Channels | 10-bit manual / 8-bit auto mode; 9 channels - provides precise system monitoring including VDD, temperature, and resistive touch sensing. |
| Operating Modes | 5 distinct modes (ACTIVE, POWERDOWN, RESET, DELIVERY, NO-POWER) with <20 µA quiescent current in lowest mode - extends battery life in always-on applications. |
| Interface | I²C (HS 2-wire) - enables real-time configuration, fault reporting, and register-level control of all regulators and GPIOs. |
| Package | 100-ball VFBGA, 8.0 mm × 8.0 mm × 1.0 mm, 0.8 mm pitch - optimized for high-density mobile PCB layouts with thermal vias under exposed pad. |
Pinout & Package
DA9063L-XXHO1-AT is packaged in a 100-ball Very Fine Pitch Ball Grid Array (VFBGA), 8.0 mm × 8.0 mm × 1.0 mm body, 0.8 mm ball pitch, 0.30 mm solder balls, with exposed thermal pad for enhanced heat dissipation. Pin functions are validated per Renesas datasheet Rev. 2.4 (pp. 8–13).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| nIRQ | Digital Output | Active-low interrupt signal to host processor indicating regulator fault, ADC threshold breach, or GPIO event. |
| VSYS | Power Input | Main system input (2.8–5.5 V); powers all internal bucks and supplies LDO input stages. |
| VBUCKCORE1 / VBUCKCORE2 | Analog Input | Core rail feedback sense nodes - enable accurate closed-loop regulation and dual-phase current balancing. |
| SWBUCKPRO_A / SWBUCKPRO_B | Analog Output | Half- and full-current switching nodes for BUCKPRO - support flexible DDR termination and split-load configurations. |
| GPIO0–GPIO15 | Digital I/O | 16 programmable pins supporting keypad scan, wakeup triggers, PWM outputs, and hardware-controlled regulator enable. |
| ADCIN1–ADCIN3 | Analog Input | Dedicated GPADC channels with hardware comparators - enable resistive touchscreen, battery voltage, and thermal sensing without host intervention. |
| nONKEY | Digital Input | Hardware on/off key detector with long-press shutdown and lock functionality - eliminates need for external microcontroller supervision. |
| VDD_IO1 / VDD_IO2 | Power Supply | Independent I/O domain supplies - allow separate voltage control for different interface groups (e.g., SDIO, USB, display). |
Key Features
| Feature | Design Value |
|---|---|
| Dual-phase BUCKCORE architecture | Enables 5 A core supply with <1% output voltage deviation across load transients and thermal gradients. |
| SmartMirror™ LDOs with cascade input | Accept 1.5–1.8 V input from buck outputs - improves overall system efficiency by >15% vs. direct battery-fed LDOs. |
| Programmable power sequencer (OTP + software) | Supports deterministic boot timing, user-defined delay slots, and fail-safe power-down sequences without host firmware involvement. |
| Integrated 9-channel ADC with alarm thresholds | Monitors critical voltages, temperature, and external sensors autonomously - reduces host polling overhead and enables predictive thermal throttling. |
| PWM-controlled vibration motor driver (LDO8) | 6-bit resolution with automatic battery voltage compensation - ensures consistent motor intensity across discharge cycle. |
| RGB-LED driver with autonomous flashing | Three dedicated PWM outputs - enable status indication without CPU cycles or external LED controller. |
Applications
| Automotive Infotainment | Mobile Application Processor Power |
|---|---|
|
Use Scenario: Powering SoC, display interface, audio codec, and connectivity modules in head-unit systems. IC Role / Device Role / Timing Role: Central system PMIC managing 7+ regulated rails, sequencing boot order, supervising thermal limits, and responding to ignition-on/off events. Use Value: Enables AEC-Q100 Grade 2 compliance, supports DDR VTT termination for LPDDR3/4 memory, and maintains <20 µA standby current during vehicle sleep mode. |
Use Scenario: Supplying dual- or quad-core application processors (e.g., i.MX series) in smartphones, tablets, and eReaders. IC Role / Device Role / Timing Role: Primary power manager delivering dynamically scaled core voltage (DVC), memory I/O, and peripheral rails with sub-µs response to load steps. Use Value: Achieves >90% peak efficiency at 2 A load using 3 MHz switching and 1 µH inductors, reducing board area by 30% vs. discrete solutions. |
| FPGA Power Management | Industrial Handheld Devices |
|
Use Scenario: Providing configurable, tightly regulated supplies for FPGA core, auxiliary, and I/O banks in portable test equipment. IC Role / Device Role / Timing Role: Multi-rail PMIC with independent enable/control per rail, ADC-based voltage margining, and programmable power-up sequencing aligned to FPGA configuration timing. Use Value: Eliminates need for 8+ discrete regulators and external sequencing ICs; supports FPGA partial reconfiguration via I²C-controlled rail toggling. |
Use Scenario: Powering ARM-based medical monitors, barcode scanners, and ruggedized IoT edge devices with extended battery life requirements. IC Role / Device Role / Timing Role: System-level PMIC handling battery charging interface supervision, button detection, LED/vibration feedback, and low-power wake-on-event operation. Use Value: Integrates watchdog, GPIO extender, and ADC into single package - reduces BOM count by 12 components and simplifies firmware power-state management. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar system PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DA9062-XXHO1-AT | 5-buck, 4-LDO variant; lacks DDR VTT mode, vibration motor driver, and one ADC channel; lower max buck current (2 A). | Suitable for simpler APs without DDR memory or haptic feedback; not AEC-Q100 qualified. | Select when cost sensitivity outweighs DDR support and automotive qualification needs. |
| TPS659122YFFR | Texas Instruments part with 6 bucks, 10 LDOs, but no integrated vibration driver or autonomous RGB flashing; uses SPI instead of I²C. | Targets TI ecosystem designs; requires external thermal sensor; lacks OTP sequencer autonomy. | Prefer when existing design uses TI power tools or requires higher LDO count over integrated haptics/LED control. |
Compared with DA9063L-XXHO1-AT, DA9062-XXHO1-AT reduces feature set and qualification scope for cost-sensitive non-automotive use, while TPS659122YFFR trades integrated peripherals for broader LDO flexibility and TI-specific toolchain support-neither offers identical AEC-Q100 Grade 2 compliance, DDR VTT, nor autonomous haptic/LED control in the same footprint.
Availability
DA9063L-XXHO1-AT is available at Aetrix Electronics and suitable for automotive infotainment, mobile application processor power, FPGA supply, and industrial handheld devices requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for DA9063L-XXHO1-AT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power management, and SoC solutions for automotive, industrial, and consumer markets.
The DA9063L-XXHO1-AT belongs to Renesas' System PMIC product line, engineered specifically for high-efficiency, multi-rail power delivery in resource-constrained mobile and automotive platforms with stringent thermal and reliability requirements.
FAQ
What is the maximum supported core supply current for DA9063L-XXHO1-AT?
The DA9063L-XXHO1-AT supports up to 5 A core supply using dual-phase operation of BUCKCORE1 and BUCKCORE2. Each buck delivers up to 2.5 A in full-current mode, and their combined operation achieves 5 A with tight current sharing and synchronized switching to minimize ripple and EMI. This capability is explicitly confirmed in the datasheet's Key Features section and Regulator Overview table.
Does DA9063L-XXHO1-AT support DDR memory bus termination?
Yes, DA9063L-XXHO1-AT supports DDR memory bus termination through BUCKPRO configured in DDR VTT supply mode. The device generates a precise 50% VDDQ reference (VTTR pin) and regulates termination voltage with fast transient response. This function is documented in the General Description, Key Features, and Section 6.10.2 of the datasheet.
Is DA9063L-XXHO1-AT qualified for automotive applications?
Yes, the DA9063L-XXHO1-AT is available in an AEC-Q100 Grade 2 qualified variant (designated DA9063L-A). This qualification covers operation from –40 °C to +105 °C ambient, robustness against automotive electrical transients, and reliability testing per AEC standards. The datasheet explicitly lists "Automotive AEC-Q100 Grade 2 available (DA9063L-A)" in the Applications section.
How many GPIOs does DA9063L-XXHO1-AT provide, and what are their capabilities?
The DA9063L-XXHO1-AT provides up to 16 freely configurable GPIO pins (GPIO0–GPIO15), supporting keypad supervision, application wakeup, PWM output, hardware-controlled regulator enable, and timing-driven peripheral control. Several GPIOs (e.g., GPIO11, GPIO14, GPIO15) offer high-power output and blinking features. These capabilities are detailed in the General Description and Pin Description tables (pp. 9–13) of the datasheet.
What ADC resolution and monitoring functions does DA9063L-XXHO1-AT support?
The DA9063L-XXHO1-AT integrates a 9-channel ADC with 10-bit resolution in manual conversion mode and 8-bit resolution in AUTO mode. It monitors system voltage, junction temperature, three general-purpose analog inputs, and includes programmable high/low thresholds, resistive measurement current source, and low-voltage warning. All specifications are confirmed in Sections 5.9 and 6.11 of the datasheet.
DA9063L-XXHO1-AT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 100-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Processor
- Current - Supply:
- 11mA
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TFBGA (8x8)
DA9063L-XXHO1-AT FAQ
1.How can I place an order for DA9063L-XXHO1-AT through Aetrix?
Please submit a Request for Quotation (RFQ) for DA9063L-XXHO1-AT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA9063L-XXHO1-AT reliable?
The price and inventory of DA9063L-XXHO1-AT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9063L-XXHO1-AT is usually 5 days.
3.What payment methods are accepted for DA9063L-XXHO1-AT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9063L-XXHO1-AT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA9063L-XXHO1-AT?
DA9063L-XXHO1-AT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA9063L-XXHO1-AT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA9063L-XXHO1-AT?
For technical support, including DA9063L-XXHO1-AT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9063L-XXHO1-AT requirements.
6.How does Aetrix verify that DA9063L-XXHO1-AT is sourced from the original manufacturer or authorized distributors?
All DA9063L-XXHO1-AT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9063L-XXHO1-AT meets industry standards.
7.What is the process for return or replacement of DA9063L-XXHO1-AT?
All DA9063L-XXHO1-AT units undergo pre-shipment inspection (PSI). If there is an issue with DA9063L-XXHO1-AT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA9063L-XXHO1-AT part is unused and in its original packaging.
Return procedure for DA9063L-XXHO1-AT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DA9063L-XXHO1-AT Tags

-
TPS2511DGNR
Texas Instruments

-
UTC2000/MG
Microchip Technology

-
TUSB320HAIRWBR
Texas Instruments

-
TPS61252DSGR
Texas Instruments

-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments

-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments

-
STUSB1600AQTR
STMicroelectronics

-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments

-
TPS65150PWPR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

