STMicroelectronics DVIULC6-2P6
- Part No.:
- DVIULC6-2P6
- Manufacturer:
- STMicroelectronics
- Category:
- TVS Diodes
- Package:
- SOT-563, SOT-666
- Datasheet:
-
DVIULC6-2P6.pdf
- Description:
- TVS DIODE 5VWM 17VC SOT666
- Quantity:
- Payment:

- Shipping:

Inventory:5,616
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Product details
Overview
DVIULC6-2P6 from STMicroelectronics is a monolithic ultra-low-capacitance ESD protection device for high-speed differential data lines, featuring 0.6 pF I/O-to-GND capacitance at 825 MHz, ±15 kV IEC 61000-4-2 air/contact discharge rating, and 12 V clamping voltage at 1 A (8/20 µs), deployed on DVI, IEEE 1394, and USB 2.0 interfaces up to 3.2 Gb/s.
For engineers reviewing the DVIULC6-2P6 datasheet, DVIULC6-2P6 pinout, DVIULC6-2P6 application, or DVIULC6-2P6 equivalent, this part delivers verified signal integrity preservation in high-bit-rate video and serial links while meeting system-level ESD immunity requirements without degrading intra-pair skew or bandwidth.
Technical Context
The DVIULC6-2P6 implements a rail-to-rail ESD clamp topology with integrated transil and forward diodes, enabling bidirectional clamping across two independent I/O lines relative to GND and VBUS. Its monolithic silicon structure ensures matched capacitance (<0.02 pF variation) and low dynamic resistance (0.5 Ω typical) for consistent transient response.
Designed specifically for TMDS and differential signaling paths, it maintains <0.5 pF inter-line capacitance and achieves –7.6 dB crosstalk suppression at 7 GHz, preserving eye diagram integrity at 1.65–3.2 Gbps as validated in application circuits with DVI single-link and IEEE 1394c layouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±15 kV air & contact discharge per IEC 61000-4-2 Level 4 - guarantees full-system immunity without external suppressors |
| I/O-to-GND Capacitance | 0.6 pF @ 825 MHz - preserves signal rise/fall times and minimizes insertion loss in >1.65 Gb/s links |
| Clamping Voltage | 12 V @ 1 A (8/20 µs) - limits downstream IC stress below 13.3 V absolute max rating of typical TMDS receivers |
| Leakage Current | 0.5 µA max @ 5 V - enables multi-year battery life in portable USB/DVI accessories |
| Breakdown Voltage | 6 V @ 1 mA - ensures no conduction during normal 3.3–5 V interface operation |
| Inter-I/O Capacitance | 0.5 pF @ 825 MHz - maintains differential impedance stability and reduces common-mode conversion |
Pinout & Package
Supplied in µQFN-6 package (1.45 × 1.00 mm, 0.5 mm pitch), with wettable flanks and ECOPACK® lead-free finish compliant with RoHS and JEDEC JESD97.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O1 (e.g., DVI D0+) | Protected high-speed differential input/output line; connects directly to connector pin |
| 2 | GND | Low-inductance return path for ESD current; must tie to solid ground plane under device |
| 3 | I/O2 (e.g., DVI D0–) | Second protected differential line; matched length and layout critical for skew control |
| 4 | VBUS | Optional 5 V supply connection for enhanced clamping when VBUS present; left open if unused |
| 5 | NC | No internal connection - must remain unconnected to prevent backdrive current on data lines |
| 6 | GND | Secondary ground terminal; improves thermal dissipation and reduces loop inductance vs. single-GND layout |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low inter-pair capacitance mismatch | ΔC ≤ 0.02 pF - ensures <0.1 ps intra-pair skew impact at 3.2 Gbps, meeting IEEE 1394c timing budgets |
| Monolithic dual-line integration | Single-die construction - eliminates inter-device parameter variation and saves 1.45 mm² PCB area vs. discrete diode arrays |
| Optimized for TMDS signal integrity | –7.6 dB crosstalk @ 7 GHz - prevents ghosting or jitter accumulation in high-resolution DVI video streams |
| Controlled ESD response time | Sub-nanosecond turn-on - clamps transients before propagation into sensitive SerDes circuitry, unlike varistors |
Applications
| DVI Single-Link Video Interface | IEEE 1394c High-Speed Serial Bus |
|---|---|
Use Scenario: Protecting TMDS clock and data channels between desktop GPU and flat-panel display. IC Role / Device Role / Timing Role: Bidirectional ESD clamp on each differential pair (CLK+/–, D0+/–, D1+/–, D2+/–), placed within 3 mm of DVI connector. Use Value: Maintains 1.65 Gb/s eye opening >80% UI with <0.5 dB insertion loss up to 1.2 GHz, verified in Figure 6. | Use Scenario: Shielding FireWire S1600/S3200 physical layer against connector-induced ESD in camcorders and audio interfaces. IC Role / Device Role / Timing Role: Per-lane protection on 16 differential pairs; VBUS pin tied to 3.3 V supply for tighter clamping. Use Value: Enables 3.2 Gb/s operation with <0.2 ps inter-pair skew deviation, satisfying IEEE 1394c jitter tolerance. |
| USB 2.0 High-Speed Port | Ethernet 1000BASE-T PHY Interface |
Use Scenario: Safeguarding D+ and D– lines on laptop USB ports exposed to frequent hot-plug events. IC Role / Device Role / Timing Role: Dual-line ESD suppressor with NC pin unconnected to avoid backdrive; placed adjacent to USB receptacle. Use Value: Delivers 480 Mb/s signal fidelity with <0.3 dB attenuation at 240 MHz, ensuring full-speed enumeration reliability. | Use Scenario: Protecting MDI-X differential pairs in industrial Ethernet switches subject to field ESD. IC Role / Device Role / Timing Role: One device per twisted pair (TX+/–, RX+/–); GND pins connected to isolated PHY ground plane. Use Value: Limits clamping overshoot to <17 V at 5 A surge, preventing PHY latch-up while maintaining 100 MHz common-mode rejection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-line ultra-low-capacitance ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | 0.8 pF I/O-GND capacitance; 15 kV contact rating only; no VBUS pin | Lacks VBUS-assisted clamping; unsuitable for DVI where VBUS presence improves clamping by ~2 V | Select when cost sensitivity outweighs VBUS-enhanced protection and layout allows higher capacitance |
| ESD56081D05 | 0.5 pF I/O-GND; ±20 kV air rating; 14 V clamping @ 1 A | Higher clamping voltage increases risk of damage to 1.2 V I/O receivers in modern SoCs | Prefer for legacy 3.3 V systems where clamping margin >14 V is acceptable |
Compared with TPD2E001DRYR and ESD56081D05, DVIULC6-2P6 uniquely balances sub-0.6 pF capacitance, VBUS-enabled clamping headroom, and matched dual-line performance-making it optimal for next-gen DVI, 1394c, and USB 2.0 designs demanding both speed and robustness.
Availability
DVIULC6-2P6 is available at Aetrix Electronics and suitable for DVI video interfaces, IEEE 1394c serial buses, and USB 2.0 high-speed ports requiring stable component supply across automotive infotainment, industrial displays, and consumer electronics production.
Supply support for DVIULC6-2P6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.
DVIULC6-2P6 belongs to ST's Ultra Low Capacitance (ULC) ESD protection product line, engineered specifically to preserve signal integrity in >1 Gb/s differential interfaces while delivering certified system-level ESD immunity.
FAQ
What is the function of Pin 5 (NC) on DVIULC6-2P6?
Pin 5 is internally unconnected and must remain floating. Connecting it risks backdrive current flow onto protected data lines during hot-plug events, potentially disrupting TMDS or USB differential signaling. The datasheet explicitly prohibits soldering or routing to this pin to maintain signal balance and prevent latch-up in source devices.
Can DVIULC6-2P6 protect both DVI and USB 2.0 interfaces simultaneously?
Yes-its 0.6 pF capacitance and 12 V clamping voltage meet signal integrity and ESD immunity requirements for both DVI (1.65 Gb/s) and USB 2.0 (480 Mb/s). Layout must follow application notes: place within 3 mm of the connector, use symmetric traces, and connect both GND pins to a low-inductance ground plane to ensure consistent performance across protocols.
How does VBUS connection affect clamping performance?
Tying Pin 4 (VBUS) to the 5 V supply lowers clamping voltage by ~2 V during positive surges due to rail-to-rail diode activation. This is critical for DVI applications where TMDS receivers have tight 13.3 V absolute maximum ratings. When VBUS is absent, clamping reverts to standard transil behavior with slightly higher VCL, as specified in Table 2.
Is DVIULC6-2P6 compatible with lead-free reflow profiles?
Yes-it is qualified for ECOPACK® lead-free assembly with a peak reflow temperature of 260 °C (max), 220 °C preheat, and 90–150 sec above 180 °C. The µQFN-6 package uses matte tin terminations and meets JEDEC J-STD-020 moisture sensitivity level 1, eliminating bake requirements prior to SMT placement.
DVIULC6-2P6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- SOT-563, SOT-666
- Series:
- DVI
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 17V
- Current - Peak Pulse (10/1000µs):
- 5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.85pF @ 825MHz
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-666
DVIULC6-2P6 FAQ
1.How can I place an order for DVIULC6-2P6 through Aetrix?
Please submit a Request for Quotation (RFQ) for DVIULC6-2P6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DVIULC6-2P6 reliable?
The price and inventory of DVIULC6-2P6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DVIULC6-2P6 is usually 5 days.
3.What payment methods are accepted for DVIULC6-2P6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DVIULC6-2P6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DVIULC6-2P6?
DVIULC6-2P6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DVIULC6-2P6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DVIULC6-2P6?
For technical support, including DVIULC6-2P6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DVIULC6-2P6 requirements.
6.How does Aetrix verify that DVIULC6-2P6 is sourced from the original manufacturer or authorized distributors?
All DVIULC6-2P6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DVIULC6-2P6 meets industry standards.
7.What is the process for return or replacement of DVIULC6-2P6?
All DVIULC6-2P6 units undergo pre-shipment inspection (PSI). If there is an issue with DVIULC6-2P6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DVIULC6-2P6 part is unused and in its original packaging.
Return procedure for DVIULC6-2P6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DVIULC6-2P6 Tags

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