My Inquiry
My Account
Microchip Technology EEC1005-I/WC-UB2
- Part No.:
- EEC1005-I/WC-UB2
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 144-WFBGA
- Datasheet:
-
EEC1005-I/WC-UB2.pdf
- Description:
- UBM CONTROLLER, 144-PIN, SFF-TA-
- Quantity:
- Payment:
- Shipping:
Inventory:149
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
EEC1005-I/WC-UB2 from Microchip Technology is a universal storage backplane management processor implementing SFF-TA-1005 UBM over I²C, supporting SFF-8654 HFC and SFF-8639/SFF-TA-1001 DFC interfaces, with hardware-accelerated SGPIO for SAS/SATA backplanes and secure boot using AES-256/ECDSA/SHA-256. It manages up to 12 NVMe drives via UBM and integrates non-volatile FRU memory per HFC for enterprise rack-mount storage enclosures.
For engineers reviewing the EEC1005-I/WC-UB2 datasheet, EEC1005-I/WC-UB2 pinout, EEC1005-I/WC-UB2 application, or EEC1005-I/WC-UB2 equivalent, key selection criteria include UBM/SGPIO interface configurability via analog CONFIG_PIN, support for PERST-driven NVMe hot-plug, SFF-8489-compliant LED management, and dual-package availability (84-pin/144-pin WFBGA) matching specific backplane drive count and protocol requirements.
Technical Context
The EEC1005-I/WC-UB2 implements a firmware-configurable UBM controller architecture that routes sideband signals (IFDET, PRSNT, PERST) between host-facing connectors (HFCs) and drive-facing connectors (DFCs), with dedicated hardware acceleration for up to four SGPIO legacy interfaces. Its configuration is determined at power-up by an analog voltage on the CONFIG_PIN, selecting among 13 predefined backplane topologies including mixed UBM+SGPIO modes.
It integrates three distinct FRU memory spaces: 256-byte Configuration FRU (I²C address 0x54), 256-byte Generic FRU (I²C address 0x54), and per-HFC UBM FRUs (I²C address 0xAE), all compliant with SFF-TA-1005 and IPMI standards. Secure boot leverages embedded AES-256, ECDSA P-256, and SHA-256 accelerators with lockable OTP for private key storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Universal Backplane Management (UBM) processor per SFF-TA-1005, supporting both I²C-based UBM and SGPIO host interfaces |
| Drive Support | Up to 12 NVMe drives via UBM HFCs; up to 16 SAS/SATA drives via SGPIO; supports U.2 and U.3 DFCs |
| Interface Count | Up to 8 I²C ports (for UBM/BMC communication); up to 4 hardware-accelerated SGPIO controllers |
| Security | Secure boot with AES-256/ECDSA P-256/SHA-256 hardware accelerators; lockable OTP for private keys; secure firmware update |
| LED Control | SFF-8489 IBPI-compliant LED management for Online/Green and Fault/Amber states; custom blink patterns programmable via FRU |
| Package | 84-pin or 144-pin RoHS-compliant WFBGA; EEC1005-I/WC-UB2 uses 144-pin WFBGA per Microchip DS00003392B |
| FRU Memory | Three independent 256-byte FRU spaces: Configuration FRU (I²C 0x54), Generic FRU (I²C 0x54), and per-HFC UBM FRUs (I²C 0xAE) |
Pinout & Package
EEC1005-I/WC-UB2 is housed in a 144-pin Wafer-Level Fine-Pitch Ball Grid Array (WFBGA) package, RoHS-compliant, with 0.5 mm pitch and 7.0 mm × 7.0 mm body size per Microchip DS00003392B, page 48. Pin functions are configuration-dependent and defined in Tables 10-1 and 10-2 of the datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CONFIG_PIN | Analog configuration input | Samples resistor-divider voltage at startup to select one of 13 supported backplane configurations (e.g., 8-Drive UBM U.3 Full Feature) |
| HFCx_IFDET#, HFCx_PRSNT#, HFCx_PERST# | Host-facing connector sideband signals | Dedicated pins per HFC for drive presence detection, insertion sensing, and PCIe reset control without latency |
| DFCx_IFDET2# | U.3-specific sideband input | Supports SFF-TA-1001 IFDET2 signal for enhanced U.3 drive identification and status reporting |
| SGPIOx_CLOCK, SGPIOx_LOAD, SGPIOx_DATA, SGPIOx_OE | SGPIO bus interface | Hardware-accelerated SGPIO lanes for SAS/SATA backplane management; up to 4 independent controllers |
| UBM_I2C_SDA/SCL | UBM management interface | I²C bus for UBM command exchange with host (SFF-TA-1005 compliant), operating at standard/fast-mode speeds |
Key Features
| Feature | Design Value |
|---|---|
| Configurable Backplane Topology | Selects among 13 pre-defined architectures (e.g., 12-Drive UBM U.2 PCIe Only) via single analog CONFIG_PIN voltage, eliminating firmware reflash for hardware variants |
| Multi-Protocol Drive Support | Simultaneous U.2 and U.3 DFC compliance with native SFF-8639 and SFF-TA-1001 electrical signaling and pinout mapping |
| Hardware-Accelerated SGPIO | Four independent SGPIO controllers with dedicated logic for SAS/SATA sideband timing, reducing host CPU overhead and enabling real-time drive status updates |
| Per-HFC UBM FRU | Integrated 256-byte read-only NVRAM per Host Facing Connector (I²C 0xAE), eliminating external EEPROM and saving PCB area per HFC |
| Secure Firmware Lifecycle | AES-256 decryption and ECDSA P-256 signature verification at boot; secure OTA updates with key revocation; TRNG for cryptographic entropy |
Applications
| Enterprise NVMe Storage Enclosures | SAS/SATA Backplane Management |
|---|---|
Use Scenario: 2U/4U rack-mount server chassis with 12–16 hot-swappable NVMe U.2/U.3 drives managed by a PCIe switch or BMC. IC Role / Device Role / Timing Role: UBM controller handling SES commands, PERST assertion/recovery, and drive presence detection via IFDET/PRSNT signals on each DFC. Use Value: Enables zero-latency NVMe drive reset and hot-plug without host OS intervention, meeting SFF-TA-1001 and SFF-8639 compliance for data center deployments. | Use Scenario: High-density JBOD with 16 SAS/SATA drives connected via SFF-8485 SGPIO cabling to a RAID controller or HBA. IC Role / Device Role / Timing Role: SGPIO controller managing sideband signals (clock/load/data/OE) across four independent lanes, driving LEDs per drive slot per SFF-8489 IBPI spec. Use Value: Hardware-accelerated SGPIO eliminates software polling delays, ensuring sub-100ms LED state updates and accurate drive activity/fault reporting. |
| Mixed-Protocol Backplanes | BMC-Managed Direct-Attach Storage |
Use Scenario: Hybrid storage backplane supporting both U.3 NVMe and SAS drives in same enclosure, requiring unified management via single controller. IC Role / Device Role / Timing Role: Dual-mode UBM/SGPIO controller configured via CONFIG_PIN to operate 4 HFCs (2 PCIe + 2 SAS) and 8 DFCs (4 U.3 + 4 SAS), sharing common FRU and LED resources. Use Value: Reduces BOM count and layout complexity versus discrete UBM + SGPIO solutions while maintaining full protocol isolation and timing compliance. | Use Scenario: Edge server with direct-attach backplane where BMC (not HBA) acts as UBM host, managing drives via I²C instead of SGPIO. IC Role / Device Role / Timing Role: I²C-based UBM endpoint responding to standard SFF-TA-1005 commands (e.g., Host Facing Connector Info, Backplane Info) over BMC I²C segment (address 0x54). Use Value: Eliminates need for HBA-side management firmware; enables BMC-centric storage health monitoring and LED control in cost-sensitive embedded systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar universal backplane management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Microchip EEC1005-I/WC-UB1 | 84-pin WFBGA package; supports fewer HFCs/DFCs (max 8 drives in UBM mode); lacks full U.3 IFDET2 support per datasheet Table 3-1 | Targeted at compact 4–8 drive SAS/NVMe enclosures with space-constrained PCBs | Select EEC1005-I/WC-UB1 only when drive count ≤8 and U.3 IFDET2 is not required |
| Microchip EEC1005-I/WC-UB3 | 144-pin WFBGA with identical pinout to EEC1005-I/WC-UB2 but factory-configured for 12-Drive UBM U.2 PCIe Only (Config ID 0A) | Optimized for PCIe-only NVMe backplanes without SAS/SATA coexistence | Choose EEC1005-I/WC-UB3 if fixed 12-drive U.2 PCIe topology is guaranteed and configuration flexibility is unnecessary |
Compared with EEC1005-I/WC-UB1, EEC1005-I/WC-UB2 offers higher drive density and U.3 IFDET2 support; compared with EEC1005-I/WC-UB3, it provides runtime-configurable topology selection via CONFIG_PIN rather than fixed factory programming, enabling one PCB design to serve multiple backplane variants.
Availability
EEC1005-I/WC-UB2 is available at Aetrix Electronics and suitable for enterprise NVMe storage enclosures, SAS/SATA JBOD backplanes, mixed-protocol storage systems, and BMC-managed direct-attach storage requiring stable component supply and long-term lifecycle support.
Supply support for EEC1005-I/WC-UB2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, FPGAs, and security ICs, serving automotive, industrial, communications, and computing markets with vertically integrated silicon and software solutions.
The EEC1005 product line delivers enterprise-grade backplane management processors designed specifically for SFF-compliant storage enclosures, enabling scalable, secure, and protocol-agnostic drive control in hyperscale data centers and edge infrastructure.
FAQ
What is the package type and pin count for EEC1005-I/WC-UB2?
EEC1005-I/WC-UB2 uses a 144-pin RoHS-compliant Wafer-Level Fine-Pitch Ball Grid Array (WFBGA) package with 0.5 mm pitch and 7.0 mm × 7.0 mm body size, as specified in Microchip DS00003392B, page 48. This package supports all 13 configuration modes, including 12-Drive and 16-Drive topologies requiring maximum I/O resources.
How does EEC1005-I/WC-UB2 support both U.2 and U.3 drive connectors?
EEC1005-I/WC-UB2 natively supports SFF-8639 (U.2) and SFF-TA-1001 (U.3) Drive Facing Connectors through dedicated DFC signal routing and IFDET2# pin support for U.3-specific identification. Its firmware configuration-selected via CONFIG_PIN voltage-enables appropriate electrical signaling, sideband handling, and FRU reporting per specification, ensuring full compliance with both form factors.
What security features does EEC1005-I/WC-UB2 provide for firmware integrity?
EEC1005-I/WC-UB2 implements hardware-accelerated secure boot using AES-256 decryption, ECDSA P-256 signature verification, and SHA-256 hashing. It includes lockable One-Time Programmable (OTP) memory for private keys and a True Random Number Generator (TRNG). Secure firmware updates and key revocation are supported, ensuring trusted execution from power-on reset.
Can EEC1005-I/WC-UB2 manage both SAS/SATA and NVMe drives on the same backplane?
Yes, EEC1005-I/WC-UB2 supports mixed-protocol backplanes via its UBM+SGPIO configuration mode (Config ID 0D). In this mode, it operates 5 HFCs (1 SAS + 4 PCIe) and 8 DFCs (8 SAS/SATA + 8 U.2/U.3), sharing LED control and FRU resources while maintaining protocol-isolated sideband signaling and command processing per SFF standards.
How is backplane configuration selected on EEC1005-I/WC-UB2?
Backplane configuration on EEC1005-I/WC-UB2 is selected at power-up by sampling an analog voltage on the CONFIG_PIN using an internal ADC. A resistor divider network sets voltages from 0.1 V to 1.3 V, each corresponding to a specific topology (e.g., 0.9 V = 8-Drive UBM U.3 Full Feature). Configuration is fixed per power cycle and cannot be changed dynamically in runtime.
EEC1005-I/WC-UB2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 144-WFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Applications:
- Storage Backplane Management
- Core Processor:
- ARM® Cortex®-M4
- Program Memory Type:
- -
- Controller Series:
- EEC1005
- RAM Size:
- -
- Interface:
- BMC, I2C, SGPIO, UBM
- Number of I/O:
- 3
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 144-WFBGA (10x10)
EEC1005-I/WC-UB2 FAQ
1.How can I place an order for EEC1005-I/WC-UB2 through Aetrix?
Please submit a Request for Quotation (RFQ) for EEC1005-I/WC-UB2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for EEC1005-I/WC-UB2 reliable?
The price and inventory of EEC1005-I/WC-UB2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for EEC1005-I/WC-UB2 is usually 5 days.
3.What payment methods are accepted for EEC1005-I/WC-UB2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for EEC1005-I/WC-UB2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for EEC1005-I/WC-UB2?
EEC1005-I/WC-UB2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your EEC1005-I/WC-UB2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for EEC1005-I/WC-UB2?
For technical support, including EEC1005-I/WC-UB2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your EEC1005-I/WC-UB2 requirements.
6.How does Aetrix verify that EEC1005-I/WC-UB2 is sourced from the original manufacturer or authorized distributors?
All EEC1005-I/WC-UB2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that EEC1005-I/WC-UB2 meets industry standards.
7.What is the process for return or replacement of EEC1005-I/WC-UB2?
All EEC1005-I/WC-UB2 units undergo pre-shipment inspection (PSI). If there is an issue with EEC1005-I/WC-UB2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The EEC1005-I/WC-UB2 part is unused and in its original packaging.
Return procedure for EEC1005-I/WC-UB2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
EEC1005-I/WC-UB2 Tags
-
CYPD3175-24LQXQ
Infineon Technologies
-
SLB9672VU20FW1523XTMA1
Infineon Technologies
-
SLB9670VQ20FW785XTMA1
Infineon Technologies
-
SLB9672XU20FW1523XTMA1
Infineon Technologies
-
SLB9673XU20FW2613XTMA1
Infineon Technologies
-
CYPD3125-40LQXIT
Infineon Technologies
-
AT97SC3204-U2A1A-20
Microchip Technology
-
AT97SC3204-U2A1A-10
Microchip Technology
-
SLM9670AQ20FW1311XTMA1
Infineon Technologies
-
SLB9672XU20FW1613XTMA1
Infineon Technologies
-
SLB9672AU20FW1613XTMA1
Infineon Technologies
-
SLB9673AU20FW2613XTMA1
Infineon Technologies
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
