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Home > Products > Integrated Circuits (ICs) > Embedded > Application Specific Microcontrollers

Microchip Technology EEC1005-I/WC-UB2-TR

Name: EEC1005-I/WC-UB2-TR
Brand: Microchip Technology
SKU: EEC1005-I/WC-UB2-TR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: EEC1005-I/WC-UB2-TR

Manufacturer:: Microchip Technology

Category:: Application Specific Microcontrollers

Package:: 144-WFBGA

Datasheet:: EEC1005-I/WC-UB2-TR.pdf

Description:: UBM CONTROLLER, 144-PIN, SFF-TA-

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Product details

Overview

EEC1005-I/WC-UB2-TR from Microchip Technology is a Universal Backplane Management (UBM) processor for enterprise storage enclosures, supporting SFF-TA-1005 Rev 1.3/1.4 over I²C, up to 6 Host Facing Connectors (HFC), and U.2/U.3 Drive Facing Connectors (DFC) for NVMe/SAS/SATA drives. It integrates secure boot with ECC P-256, hardware-accelerated crypto, and FRU memory for HFC, configuration, and generic use.

For engineers reviewing the EEC1005-I/WC-UB2-TR datasheet, EEC1005-I/WC-UB2-TR pinout, EEC1005-I/WC-UB2-TR application, or EEC1005-I/WC-UB2-TR equivalent, this device serves as a configurable backplane controller enabling SES-over-UBM, NVMe hot-plug/power-disable, Intel VPP support, EDSFF compatibility, and IBPI 2-/3-LED LED management in high-density server and storage systems.

Technical Context

The EEC1005-I/WC-UB2-TR implements dual-mode host interface support-configurable at startup via analog CONFIG_PIN voltage (0.3V–2.3V)-to select among 21 UB2-specific configurations including SGPIO-only (16-drive SAS/SATA), UBM-only (12-drive U.3 PCIe), or hybrid UBM+SGPIO topologies. Each configuration defines HFC count (up to 6), DFC count (up to 12), and lane mapping (x1/x2/x4 U.3).

It embeds six independent UBM controllers (UBM0–UBM5), each with dedicated I²C address space (0xD0–0xDA), FRU access (0xAE–0xB8), and hardware-peripheral signals including PERST#, IFDET#, PRSNT#, and optional IFDET2# for SFF-TA-1001 compliance. BMC-tunneled I²C emulation enables virtualized UBM command routing over a single BMC I²C bus.

Key Specifications

Parameter	Value and Actual Design Meaning
UBM Spec Support	SFF-TA-1005 Revision 1.3 and 1.4 - enables full backward compatibility with legacy UBM hosts and new features like Intel VPP and EDSFF SMBRST#.
Drive Support Capacity	Up to 12 NVMe drives via UBM interfaces or 16 SAS/SATA drives via SGPIO - scalable per configuration without firmware reflash.
Host Interface Options	Configurable I²C or SGPIO per HFC; supports BMC-tunneled I²C emulation using virtual addresses (0xD0–0xDA for controllers, 0xAE–0xB8 for FRUs).
Secure Boot & Crypto	AES-256, ECDSA P-256, SHA-256 hardware accelerators + TRNG - ensures authenticated flash boot image loading and secure firmware updates.
FRU Memory Integration	Dedicated non-volatile memory for UBM FRU (per HFC), Configuration FRU (256-byte), and Generic FRU - eliminates external EEPROMs and simplifies BOM.
LED Management	IBPI-compliant 2-LED and 3-LED patterns per drive; customizable blink timing and state behavior via Configuration FRU fields (0xBD–0xBF).
Package	144-pin WFBGA (RoHS compliant) - optimized for high-density backplane PCB layouts with thermal pad grounding and fine-pitch interconnect.

Pinout & Package

EEC1005-I/WC-UB2-TR is housed in a 144-pin Wafer-Level Fine-Pitch Ball Grid Array (WFBGA) package with 0.5 mm pitch and exposed thermal pad. Pin functions are configuration-dependent; primary signal groups include I²C buses (UBM0–UBM5, BMC), SGPIO lanes (up to 4 hardware-accelerated controllers), HFC/DFC sideband signals (PERST#, IFDET#, PRSNT#, IFDET2#), CONFIG_PIN ADC input, and crypto/security control pins.

Pin/Terminal	Circuit Role	Design Meaning
CONFIG_PIN	Analog configuration input	Voltage level (0.3–2.3 V) selects one of 21 UB2-specific backplane configurations at power-up; sets HFC count, DFC count, interface mode, and feature enablement.
HFCn_PERST#	NVMe reset control output	Active-low PERST signal per Host Facing Connector; enables direct host-driven NVMe drive reset without latency or external logic.
DFCm_IFDET# / DFCm_PRSNT#	Drive presence detection inputs	Dual-signal detection (IFDET# + PRSNT#) per Drive Facing Connector confirms physical insertion and electrical readiness of U.2/U.3 drives.
DFCm_IFDET2#	EDSFF/SFF-TA-1001 detection input	Secondary interface detect for EDSFF form factor compliance; required for U.3 x1/x2 lane configurations and SMBRST# support.
UBMn_SCL / UBMn_SDA	UBM controller I²C interface	Dedicated I²C bus per UBM controller (UBM0–UBM5); supports standard UBM commands and tunneled BMC routing via virtual addresses.
BMC_SCL / BMC_SDA	Baseboard Management Controller I²C	Primary interface for BMC communication; carries tunneled UBM/FRU traffic, Configuration FRU reads, and secure update commands.

Key Features

Feature	Design Value
UB2-exclusive SFF-TA-1005 Rev 1.4 support	Enables Intel VPP signaling, EDSFF SMBRST#, and U.3 x1/x2 lane configurations not available in UB1 variants.
Hardware-accelerated SGPIO	Four independent SGPIO controllers handle up to 16 SAS/SATA drives with zero CPU overhead and deterministic timing.
Configurable multi-HFC architecture	Supports up to 6 HFCs with independent UBM controllers, allowing single-chassis management of multiple backplanes or Y-cable split topologies.
Integrated FRU memory subsystem	On-die non-volatile storage for UBM FRU (per HFC), Configuration FRU (256-byte), and Generic FRU - reduces component count and improves reliability.
Secure firmware lifecycle	Hardware-enforced secure boot, encrypted firmware updates, key revocation, and lockable OTP storage for private keys ensure supply-chain integrity.
IBPI 2-/3-LED pattern flexibility	Runtime-configurable LED blink periods, activity states, and fault interpretations via Configuration FRU - meets SFF-8489 and custom OEM requirements.

Applications

Enterprise NVMe Storage Enclosure	Multi-Protocol SAS/SATA/NVMe Backplane
Use Scenario: High-density 1U/2U rack-mount server with 12× U.3 NVMe drives and dual HFCs for PCIe bifurcation. IC Role / Device Role / Timing Role: UBM controller managing drive presence, PERST#, power disable, and SES tunneling over I²C to host BMC. Use Value: Enables hot-plug, drive-level reset control, and standardized enclosure services without external CPLD or microcontroller.	Use Scenario: Hybrid backplane supporting 8× SAS/SATA drives and 4× U.2 NVMe drives in same chassis with shared LED indicators. IC Role / Device Role / Timing Role: Dual-mode controller running SGPIO for SAS/SATA and UBM for U.2, synchronizing LED status across protocols via IBPI. Use Value: Eliminates protocol translation logic and reduces bill-of-materials by unifying management under one IC with configurable pinout.
EDSFF Form Factor Server	BMC-Tunneled Storage Management
Use Scenario: Next-generation data center server using E1.L/E3.S EDSFF SSDs with SMBRST# and VPP signaling requirements. IC Role / Device Role / Timing Role: UBM controller providing IFDET2#, VPP address mapping, and SMBRST# assertion per DFC for EDSFF compliance. Use Value: Meets SFF-TA-1001 and SFF-TA-1009 requirements natively - no external level shifters or glue logic needed.	Use Scenario: Motherboard-integrated BMC managing multiple backplanes via single I²C bus without dedicated UBM wiring. IC Role / Device Role / Timing Role: Endpoint for BMC-tunneled I²C commands; routes virtual addresses (0xD0–0xDA) to correct UBM controller or FRU. Use Value: Reduces motherboard trace count and simplifies system-level I²C topology while maintaining full UBM functionality.

Enterprise NVMe Storage Enclosure

Multi-Protocol SAS/SATA/NVMe Backplane

Use Scenario: High-density 1U/2U rack-mount server with 12× U.3 NVMe drives and dual HFCs for PCIe bifurcation.

IC Role / Device Role / Timing Role: UBM controller managing drive presence, PERST#, power disable, and SES tunneling over I²C to host BMC.

Use Value: Enables hot-plug, drive-level reset control, and standardized enclosure services without external CPLD or microcontroller.

Use Scenario: Hybrid backplane supporting 8× SAS/SATA drives and 4× U.2 NVMe drives in same chassis with shared LED indicators.

IC Role / Device Role / Timing Role: Dual-mode controller running SGPIO for SAS/SATA and UBM for U.2, synchronizing LED status across protocols via IBPI.

Use Value: Eliminates protocol translation logic and reduces bill-of-materials by unifying management under one IC with configurable pinout.

EDSFF Form Factor Server

BMC-Tunneled Storage Management

Use Scenario: Next-generation data center server using E1.L/E3.S EDSFF SSDs with SMBRST# and VPP signaling requirements.

IC Role / Device Role / Timing Role: UBM controller providing IFDET2#, VPP address mapping, and SMBRST# assertion per DFC for EDSFF compliance.

Use Value: Meets SFF-TA-1001 and SFF-TA-1009 requirements natively - no external level shifters or glue logic needed.

Use Scenario: Motherboard-integrated BMC managing multiple backplanes via single I²C bus without dedicated UBM wiring.

IC Role / Device Role / Timing Role: Endpoint for BMC-tunneled I²C commands; routes virtual addresses (0xD0–0xDA) to correct UBM controller or FRU.

Use Value: Reduces motherboard trace count and simplifies system-level I²C topology while maintaining full UBM functionality.

Equivalent & Alternatives

The following parts are listed as comparable options for similar universal backplane management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
EEC1005-I/WC-UB1-TR	Supports only SFF-TA-1005 Rev 1.3; lacks Intel VPP, EDSFF IFDET2#, U.3 x1/x2 lanes, and IBPI 3-LED mode.	Restricted to legacy U.2/U.3 x4 and SAS/SATA backplanes without EDSFF or advanced power management.	Select UB1 only for cost-sensitive, non-EDSFF deployments where Rev 1.4 features are unnecessary.
Microchip LAN9668-ABZ	8-port managed Ethernet switch with integrated UBM-like I²C slave; no native SGPIO, PERST#, or FRU memory.	Used in network-attached storage (NAS) with Ethernet-based enclosure management rather than direct PCIe/SAS backplane control.	Choose LAN9668 only when backplane management must coexist with Gigabit Ethernet switching on same SoC.

Compared with EEC1005-I/WC-UB1-TR, the EEC1005-I/WC-UB2-TR adds critical EDSFF and U.3 x1/x2 support, while the LAN9668-ABZ trades dedicated storage-sideband control for Ethernet integration - making UB2 the sole option for high-fidelity, standards-compliant NVMe backplane management.

Availability

EEC1005-I/WC-UB2-TR is available at Aetrix Electronics and suitable for enterprise server design, NVMe storage enclosure production, and EDSFF infrastructure development requiring stable component supply, long-term lifecycle support, and qualified industrial-grade packaging.

Supply support for EEC1005-I/WC-UB2-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a global semiconductor company specializing in microcontrollers, analog devices, FPGAs, and storage interface solutions for industrial, automotive, and datacenter markets.

The EEC1005 family was designed specifically for standards-compliant, scalable backplane management in high-density enterprise storage systems - addressing UBM, SES, SGPIO, and emerging EDSFF requirements with integrated security and configurability.

FAQ

What distinguishes EEC1005-I/WC-UB2-TR from the UB1 variant?

The EEC1005-I/WC-UB2-TR adds SFF-TA-1005 Revision 1.4 support, Intel VPP signaling, EDSFF IFDET2# and SMBRST# handling, U.3 x1/x2 lane configurations, IBPI 3-LED mode, and LED test functionality - all absent in UB1. These enhancements enable compliance with next-generation EDSFF and U.3 specifications while maintaining full backward compatibility with Rev 1.3 systems.

How does the CONFIG_PIN voltage determine EEC1005-I/WC-UB2-TR functionality?

The CONFIG_PIN analog input (0.3–2.3 V) selects one of 21 predefined UB2 configurations at power-up, defining HFC count (up to 6), DFC count (up to 12), interface type (SGPIO vs UBM), lane mapping (x1/x2/x4), and feature enablement (e.g., PERST#, VPP, IFDET2#). Resistor divider values are specified in Microchip DS00003392F Table 3-2.

Does EEC1005-I/WC-UB2-TR support secure firmware updates?

Yes. The EEC1005-I/WC-UB2-TR implements hardware-accelerated secure boot using ECDSA P-256 and SHA-256, plus encrypted firmware updates with key revocation capability. Private keys are stored in lockable OTP memory, and the TRNG ensures cryptographically secure key generation during provisioning.

Can EEC1005-I/WC-UB2-TR manage both SAS/SATA and NVMe drives simultaneously?

Yes. The EEC1005-I/WC-UB2-TR supports hybrid configurations such as "8 Drive UBM+SGPIO U.2" (Config ID 0x0D), where SGPIO handles up to 16 SAS/SATA drives and UBM manages up to 12 NVMe drives - all under unified LED control and FRU reporting via a single device.

What is the role of BMC-tunneled I²C in EEC1005-I/WC-UB2-TR systems?

BMC-tunneled I²C allows the Baseboard Management Controller to route UBM and FRU commands over its existing I²C bus instead of requiring dedicated UBM I²C traces. The EEC1005-I/WC-UB2-TR uses virtual addresses (e.g., 0xD0–0xDA for controllers, 0xAE–0xB8 for FRUs) to demultiplex traffic - reducing PCB complexity and enabling flexible backplane topologies.

EEC1005-I/WC-UB2-TR Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 144-WFBGA

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: -

Applications:: Storage Backplane Management

Core Processor:: ARM® Cortex®-M4

Program Memory Type:: -

Controller Series:: EEC1005

RAM Size:: -

Interface:: I2C, BMC, SGPIO, UBM

Number of I/O:: 3

Voltage - Supply:: 3.135V ~ 3.465V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 144-WFBGA (10x10)

EEC1005-I/WC-UB2-TR FAQ

1.How can I place an order for EEC1005-I/WC-UB2-TR through Aetrix?

Please submit a Request for Quotation (RFQ) for EEC1005-I/WC-UB2-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for EEC1005-I/WC-UB2-TR reliable?

The price and inventory of EEC1005-I/WC-UB2-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for EEC1005-I/WC-UB2-TR is usually 5 days.

3.What payment methods are accepted for EEC1005-I/WC-UB2-TR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for EEC1005-I/WC-UB2-TR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for EEC1005-I/WC-UB2-TR?

EEC1005-I/WC-UB2-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your EEC1005-I/WC-UB2-TR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for EEC1005-I/WC-UB2-TR?

For technical support, including EEC1005-I/WC-UB2-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your EEC1005-I/WC-UB2-TR requirements.

6.How does Aetrix verify that EEC1005-I/WC-UB2-TR is sourced from the original manufacturer or authorized distributors?

All EEC1005-I/WC-UB2-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that EEC1005-I/WC-UB2-TR meets industry standards.

7.What is the process for return or replacement of EEC1005-I/WC-UB2-TR?

All EEC1005-I/WC-UB2-TR units undergo pre-shipment inspection (PSI). If there is an issue with EEC1005-I/WC-UB2-TR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The EEC1005-I/WC-UB2-TR part is unused and in its original packaging.

Return procedure for EEC1005-I/WC-UB2-TR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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