STMicroelectronics FERD20S100SB-TR

Overview

FERD20S100SB-TR from STMicroelectronics is a 100 V field-effect rectifier diode in DPAK package, delivering 20 A average forward current, 0.415 V max forward voltage at 20 A/125 °C, 110 µA max reverse leakage at 25 °C/V_RRM, and 1.3 °C/W junction-to-case thermal resistance. It replaces Schottky diodes in high-efficiency, thermally constrained AC/DC adapters and server VRMs.

For engineers reviewing the FERD20S100SB-TR datasheet, FERD20S100SB-TR pinout, FERD20S100SB-TR application, or FERD20S100SB-TR equivalent, key selection criteria include VF/IR trade-off stability over temperature, thermal runaway mitigation, conduction loss modeling (P = 0.45 × I_F(AV) + 0.021 × I_F(RMS)²), and DPAK footprint compatibility with FR4 PCB copper area ≥ 90 cm².

Technical Context

This device uses ST's proprietary field-effect rectifier process to decouple forward voltage (VF) and reverse leakage (IR) dependencies on junction temperature-reducing thermal runaway risk versus conventional Schottkys. Its VF remains stable across 25–125 °C, and IR increases only modestly under 70 V reverse bias at 125 °C (3–6 mA).

Designed for confined-casing power supplies, it operates reliably up to 175 °C junction temperature with 1.3 °C/W R_th(j-c), enabling compact heatsink integration. The DPAK variant supports 150 A non-repetitive surge current (t_p = 10 ms, sinusoidal) and meets ECOPACK®2 environmental compliance.

Key Specifications

Pinout & Package

DPAK (TO-252) package: surface-mount, 3-terminal, single-tab configuration with exposed cathode pad for thermal and electrical connection. Tab is electrically connected to cathode (K).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar field-effect rectifier applications.

Compared with STTH2010D and MBR20100CT, FERD20S100SB-TR delivers superior thermal stability and lower conduction loss at elevated temperature-making it optimal for space-constrained, passively cooled power stages where long-term reliability trumps peak-room-temperature efficiency.

Availability

FERD20S100SB-TR is available at Aetrix Electronics and suitable for server VRMs, industrial AC/DC adapters, telecom power shelves, and automotive OBC auxiliary supplies requiring stable component supply, consistent thermal performance, and ECOPACK®2 compliance.

Supply support for FERD20S100SB-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.

This device belongs to ST's Field-Effect Rectifier (FERD) product line-engineered specifically to replace Schottky diodes in high-efficiency, thermally demanding power conversion applications where VF/IR trade-off stability is critical.

FAQ

What is the recommended PCB copper area for thermal performance?

The DPAK package requires ≥90 cm² of 35 µm-thick copper on FR4 board under the tab to achieve the specified R_th(j-a) of 40 °C/W. This area must be solid, unbroken, and directly soldered to the tab-thermal vias to inner layers are not sufficient alone.

Can FERD20S100SB-TR replace a Schottky diode in an existing design without layout changes?

Yes-if the original Schottky uses a DPAK footprint and shares identical anode/cathode pinout. However, verify that the lower V_F does not cause unexpected current sharing imbalance in paralleled configurations, and confirm that the reduced I_R does not affect snubber timing in RCD clamp circuits.

What is the maximum allowable mounting torque for the DPAK tab?

DPAK has no mechanical mounting screw-torque specification applies only to TO-220AB variants. For DPAK, ensure uniform solder paste deposition and reflow profile per IPC-J-STD-020; excessive localized pressure during placement may deform leads or lift the tab from the pad.

How does the conduction loss equation P = 0.45 × I_F(AV) + 0.021 × I_F(RMS)² relate to real-world efficiency?

This empirical equation models total conduction loss across operating conditions: 0.45 × I_F(AV) captures linear resistive loss, while 0.021 × I_F(RMS)² accounts for nonlinear VF curvature. It matches measured data within ±5% for 10–100 kHz switching frequencies and δ = 0.3–0.5 duty cycles.