My Inquiry
My Account
Vishay General Semiconductor - Diodes Division GSOT04C-G3-18
- Part No.:
- GSOT04C-G3-18
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
GSOT04C-G3-18.pdf
- Description:
- TVS DIODE 4VWM 14.3VC SOT23
- Quantity:
- Payment:
- Shipping:
Inventory:3,782
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
GSOT04C-G3-18 from Vishay Semiconductors is a two-line bidirectional asymmetrical ESD protection diode in SOT-23 package, rated for ±30 kV IEC 61000-4-2 contact/air discharge, 4 V reverse stand-off voltage (VRWM), and 30 A peak pulse current (IPPM) per line-to-ground path. It serves as primary transient suppression for USB 2.0 data lines, HDMI hot-plug interfaces, and industrial sensor I/O.
For engineers reviewing the GSOT04C-G3-18 datasheet, GSOT04C-G3-18 pinout, GSOT04C-G3-18 application, or GSOT04C-G3-18 equivalent, key selection criteria include its BiAs-mode clamping asymmetry, 310–450 pF capacitance at 0 V bias, 11.2–14.3 V clamping voltage at 30 A, AEC-Q101 qualification option, and SOT-23 footprint compatibility with space-constrained PCB layouts.
Technical Context
The GSOT04C-G3-18 implements BiAs-MODE (Bidirectional Asymmetrical) protection: pins 1 and 2 connect to protected signal lines (L1/L2), pin 3 to ground, enabling independent high-isolation reverse blocking (VRWM = 4 V) and low-forward-voltage clamping (VF ≤ 4.5 V at 30 A). Its dual-diode structure allows parallel use of both paths to double surge current handling while halving effective series impedance.
It supports two distinct configurations: two-line protection (pin 3 grounded, pins 1/2 on signals) with asymmetrical clamping, or single-line symmetrical protection (pin 3 unconnected, pins 1–2 across signal–ground) with matched positive/negative clamping defined by VBR + VF. Both modes comply with IEC 61000-4-2 and AEC-Q101 H3B (>8 kV HBM).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±30 kV contact & air discharge per IEC 61000-4-2 - meets Level 4 immunity for consumer/industrial ports |
| Reverse Stand-off Voltage | 4 V - ensures no leakage or interference on 3.3 V logic/data lines during normal operation |
| Peak Pulse Current | 30 A per line-to-ground path (8/20 μs) - handles severe lightning-induced surges in automotive/industrial environments |
| Clamping Voltage | 11.2–14.3 V at 30 A - limits transient overvoltage to safe levels for 5 V-tolerant interface ICs |
| Capacitance | 310–450 pF at 0 V, 200 pF at 2 V - optimized for USB 2.0 (≤450 pF) without signal integrity degradation |
| Operating Temperature | −55 °C to +150 °C - supports under-hood automotive and industrial control applications |
| AEC-Q101 Qualified | Available in AEC-Q101 qualified version - enables use in automotive infotainment and body electronics |
Pinout & Package
SOT-23 package (JEDEC TO-236AB), 3-pin surface-mount, 2.8 × 2.35 × 1.15 mm, MSL level 1, lead (Pb)-free e3 Sn plating, compatible with standard reflow profiles (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Line 1 Anode/Cathode | Connects to first protected signal (e.g., USB D+); forms one half of BiAs protection path to ground (pin 3) |
| Pin 2 | Line 2 Anode/Cathode | Connects to second protected signal (e.g., USB D−); forms second half of BiAs protection path to ground (pin 3) |
| Pin 3 | Ground Reference | Must be connected to system ground plane; provides common return for both ESD current paths |
Key Features
| Feature | Design Value |
|---|---|
| BiAs-MODE Protection | Enables independent 4 V stand-off on two data lines with asymmetrical clamping-ideal for differential interfaces like USB/HDMI |
| Parallel Path Capability | Both internal diodes can be used in parallel to double IPPM (to 60 A) and reduce clamping voltage via lower effective series impedance |
| Low Forward Clamping | VF ≤ 4.5 V at 30 A ensures negative transients are clamped near ground-critical for protecting CMOS inputs |
| SOT-23 Footprint | Standard 3-pin package allows drop-in replacement in existing designs and automated assembly with no layout change |
| AEC-Q101 Option | Qualified variant available for automotive applications requiring validated reliability and stress testing per AEC standard |
Applications
| USB 2.0 Interface Protection | HDMI Hot-Plug Detection Line |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 ports against ESD events during cable insertion/removal in portable and industrial equipment. IC Role / Device Role / Timing Role: Two-line asymmetrical transient voltage suppressor placed directly at connector, shunting ESD current to ground before it reaches USB transceiver. Use Value: 4 V VRWM prevents loading of 3.3 V data lines; 310–450 pF capacitance maintains signal integrity up to 480 Mbps without eye diagram degradation. | Use Scenario: Safeguarding the HDMI HPD (Hot-Plug Detect) line against user-induced ESD during display connection in AV receivers and set-top boxes. IC Role / Device Role / Timing Role: Single-point clamping device between HPD signal and ground, operating in BiSy mode (pin 3 open) to provide symmetrical ±30 kV protection. Use Value: 4.5 V VRWM matches typical HPD pull-up voltage; <200 pF capacitance at 2 V bias avoids false HPD toggling during high-speed plug detection. |
| Automotive Sensor I/O Protection | Industrial RS-485 Transceiver Interface |
Use Scenario: Shielding analog/digital I/O lines of pressure, temperature, or position sensors in engine control units and ADAS modules. IC Role / Device Role / Timing Role: Dual-channel ESD clamp on sensor signal pairs (e.g., CAN-L/CAN-H auxiliary lines or LIN bus), grounded via chassis or signal ground. Use Value: −55 °C to +150 °C operating range supports under-hood placement; AEC-Q101 qualification ensures long-term reliability in vibration/thermal cycling environments. | Use Scenario: Protecting RS-485 transceiver A/B differential lines against ESD and fast transients in factory automation and building management systems. IC Role / Device Role / Timing Role: Two-line BiAs protector with pins 1/2 on A/B lines and pin 3 tied to local ground, providing independent clamping for each polarity. Use Value: 30 A IPPM withstands induced surges on long cable runs; 11.2–14.3 V VC at full current prevents latch-up or damage to ±7 V-rated transceivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| VGSOT04C-G3-18 | Successor series with identical SOT-23 footprint, same VRWM (4 V), but improved 10000-cycle ESD robustness and extended -65 °C to +175 °C rating | Drop-in replacement for new designs; not recommended for legacy production due to different qualification baseline | Select for new automotive or high-reliability industrial programs where extended temperature and lifecycle are required |
| SMF4.0A | Single-line 4 V TVS diode in SOD-123; lacks dual-line integration and BiAs functionality; higher 500 pF capacitance | Requires two devices for dual-line protection; unsuitable for tightly spaced differential pairs due to layout area and coupling | Use only when board space permits discrete placement and cost sensitivity outweighs integration benefits |
Compared with VGSOT04C-G3-18, the original GSOT04C-G3-18 offers proven field reliability but reaches end-of-life in January 2025; versus SMF4.0A, it delivers integrated dual-line protection with lower capacitance and smaller footprint-critical for high-speed serial interfaces.
Availability
GSOT04C-G3-18 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive sensor I/O safeguarding, and industrial RS-485 transceiver hardening requiring stable component supply through Q1 2025.
Supply support for GSOT04C-G3-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in power management, sensing, and circuit protection components with emphasis on reliability and performance.
The GSOTxxC family was engineered specifically for high-density, high-speed data line ESD protection in automotive, industrial, and consumer electronics-balancing low capacitance, precise clamping, and robust surge handling in miniature packages.
FAQ
What is the maximum reverse working voltage (VRWM) of the GSOT04C-G3-18?
The GSOT04C-G3-18 has a maximum reverse working voltage (VRWM) of 4 V when configured in two-line BiAs mode (pins 1 and 2 to signals, pin 3 to ground). This ensures reliable isolation of 3.3 V data lines during normal operation without leakage or signal distortion. The value is confirmed in the Electrical Characteristics table for GSOT04C on page 6 of Vishay document 85824.
Can the GSOT04C-G3-18 be used for single-line symmetrical protection?
Yes, the GSOT04C-G3-18 supports BiSy-MODE (bidirectional symmetrical) operation: leave pin 3 unconnected, and use pins 1 and 2 across a single signal–ground pair. In this configuration, it delivers matched clamping for positive and negative transients, with VRWM = 4.5 V and clamping voltage ≤18.8 V at 30 A. This mode is documented on page 8 of Vishay document 85824.
What is the clamping voltage of the GSOT04C-G3-18 at 30 A peak pulse current?
At 30 A peak pulse current (8/20 μs waveform), the GSOT04C-G3-18 exhibits a reverse clamping voltage (VC) of 11.2–14.3 V when protecting a signal line to ground (pin 1–3 or pin 2–3). This value is measured per IEC 61000-4-5 and guarantees safe voltage limiting for downstream 5 V-tolerant interface ICs, as specified in the Absolute Maximum Ratings table on page 2 of document 85824.
Is the GSOT04C-G3-18 qualified to AEC-Q101?
The GSOT04C-G3-18 is offered in an AEC-Q101 qualified version (marked with "H" prefix, e.g., HGSOT04C-G3-18). The base GSOT04C-G3-18 is standard-qualified; AEC-Q101 compliance requires explicit ordering of the "H" variant. Qualification covers temperature cycling, humidity testing, and HBM ESD ≥8 kV, as noted in the Ordering Information section on page 1 of document 85824.
What is the end-of-life timeline for the GSOT04C-G3-18?
Vishay has announced end-of-life for the GSOT04C-G3-18 in January 2025, as stated in the header of document 85824 (Rev. 3.0, 13-Feb-2025). Customers are advised to transition to the VGSOTxxC series (e.g., VGSOT04C-G3-18), which shares the same SOT-23 footprint and electrical specifications while offering extended temperature range and enhanced ESD durability.
GSOT04C-G3-18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 4V (Max)
- Voltage - Breakdown (Min):
- 5V
- Voltage - Clamping (Max) @ Ipp:
- 14.3V
- Current - Peak Pulse (10/1000µs):
- 30A (8/20µs)
- Power - Peak Pulse:
- 429W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 310pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
GSOT04C-G3-18 FAQ
1.How can I place an order for GSOT04C-G3-18 through Aetrix?
Please submit a Request for Quotation (RFQ) for GSOT04C-G3-18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GSOT04C-G3-18 reliable?
The price and inventory of GSOT04C-G3-18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GSOT04C-G3-18 is usually 5 days.
3.What payment methods are accepted for GSOT04C-G3-18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GSOT04C-G3-18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GSOT04C-G3-18?
GSOT04C-G3-18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GSOT04C-G3-18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GSOT04C-G3-18?
For technical support, including GSOT04C-G3-18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GSOT04C-G3-18 requirements.
6.How does Aetrix verify that GSOT04C-G3-18 is sourced from the original manufacturer or authorized distributors?
All GSOT04C-G3-18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GSOT04C-G3-18 meets industry standards.
7.What is the process for return or replacement of GSOT04C-G3-18?
All GSOT04C-G3-18 units undergo pre-shipment inspection (PSI). If there is an issue with GSOT04C-G3-18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GSOT04C-G3-18 part is unused and in its original packaging.
Return procedure for GSOT04C-G3-18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
GSOT04C-G3-18 Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
