Vishay General Semiconductor - Diodes Division GSOT04-E3-18
- Part No.:
- GSOT04-E3-18
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
GSOT04-E3-18.pdf
- Description:
- TVS DIODE 4VWM 14.3VC SOT23
- Quantity:
- Payment:

- Shipping:

Inventory:10,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
GSOT04-E3-18 from Vishay Semiconductors is a single-line bidirectional asymmetrical (BiAs) ESD protection diode in SOT-23 package, rated for ±30 kV IEC 61000-4-2 contact/air discharge, 4 V reverse stand-off voltage (VRWM), and 429 W peak pulse power (PPP) per IEC 61000-4-5. It protects high-speed data lines such as USB 2.0 interfaces against transient overvoltage events.
For engineers reviewing the GSOT04-E3-18 datasheet, GSOT04-E3-18 pinout, GSOT04-E3-18 application, or GSOT04-E3-18 equivalent, key selection criteria include clamping voltage at 30 A (11.2–14.3 V), low capacitance (310–450 pF at 0 V), AEC-Q101 qualification option, SOT-23 footprint compatibility, and BiAs-mode operation enabling asymmetric clamping for signal integrity preservation.
Technical Context
The GSOT04-E3-18 implements BiAs-MODE (Bidirectional Asymmetrical) protection: pin 1 is grounded, pin 3 connects to the protected line, and clamping occurs at different voltage thresholds in forward (≤4.5 V @ 30 A) versus reverse (≤14.3 V @ 30 A) directions. This architecture minimizes signal distortion on low-voltage data paths while maintaining robust ESD immunity.
It operates across –40 °C to +125 °C junction temperature, complies with AEC-Q101 when specified with 'H' prefix, and uses Sn (e3) matte tin plating. The device exhibits 20 μA max reverse leakage at 4 V and 310–450 pF capacitance at 0 V bias - critical for preserving signal rise/fall times in 480 Mbps USB 2.0 applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±30 kV contact/air discharge per IEC 61000-4-2 - meets highest industrial and automotive ESD immunity requirements without external shielding. |
| Reverse Stand-off Voltage (VRWM) | 4 V - ensures no conduction during normal 3.3 V logic-level signaling, preventing false triggering or DC loading. |
| Peak Pulse Power (PPP) | 429 W @ 8/20 μs waveform - sustains high-energy transients from IEC 61000-4-5 surge tests without degradation. |
| Clamping Voltage (VC) | 11.2–14.3 V @ 30 A IPPM - limits voltage seen by downstream ICs to safe levels during worst-case ESD events. |
| Capacitance | 310–450 pF @ 0 V, 1 MHz - optimized for USB 2.0 eye diagram compliance; lower than GSOT03 but higher than GSOT05/GSOT08. |
| Leakage Current | ≤20 μA @ VR = 4 V - avoids signal integrity loss or battery drain in always-on portable interfaces. |
| Package | SOT-23 - industry-standard 3-pin footprint (2.8 × 2.35 × 1.15 mm), compatible with automated pick-and-place and reflow soldering (MSL level 1). |
Pinout & Package
SOT-23 package: 3-pin surface-mount device with standard lead pitch (0.95 mm), body dimensions 2.8 mm × 2.35 mm × 1.15 mm, and e3 matte tin (Sn) termination. MSL level 1 per J-STD-020; peak reflow temperature 260 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Ground (GND) | Low-impedance return path for ESD current; must be connected to clean system ground plane with minimal trace inductance. |
| Pin 2 | No Connection (NC) | Internally unconnected; left floating or tied to ground per layout best practice - no functional role in protection path. |
| Pin 3 | Protected Line (L1) | Input/output terminal for data/signal line (e.g., USB D+); clamps transients to ground via BiAs-mode diode structure. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional Asymmetrical (BiAs) Clamping | Forward clamping ≤4.5 V @ 30 A and reverse clamping ≤14.3 V @ 30 A - preserves low-voltage signal margins while limiting surge energy. |
| AEC-Q101 Qualification Option | Available with 'H' prefix (e.g., GSOT04-HE3-18) - validated for automotive under-hood and infotainment ESD protection. |
| e3 Matte Tin Termination | RoHS-compliant Sn plating - eliminates lead-based solder concerns and supports Pb-free reflow profiles without whisker risk. |
| Low Capacitance at Operating Bias | 200 pF typical @ VR = 2 V - maintains signal integrity on 480 Mbps USB 2.0 channels with minimal jitter or attenuation. |
| High Surge Robustness | 30 A peak pulse current (IEC 61000-4-5, 8/20 μs) - withstands repeated surge events without parameter shift or failure. |
Applications
| USB 2.0 Interface Protection | Automotive Infotainment Data Lines |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 ports in automotive head units against ESD from user contact or cable coupling. IC Role / Device Role / Timing Role: Single-line BiAs ESD suppressor placed directly at connector, shunting transients before they reach USB transceiver IC. Use Value: Prevents lockup or damage to USB PHY while maintaining <1 ns signal delay and full 480 Mbps bandwidth due to 310–450 pF capacitance. | Use Scenario: Safeguarding LVDS or UART lines between display module and main controller in ADAS dashboards exposed to cabin ESD. IC Role / Device Role / Timing Role: Point-of-entry transient suppressor on 3.3 V logic lines, leveraging AEC-Q101-qualified variants for automotive reliability. Use Value: Enables compliance with ISO 10605 (330 Ω/150 pF) and prevents firmware corruption caused by >8 kV HBM discharges. |
| Industrial Human-Machine Interface (HMI) | Medical Patient Monitoring Ports |
Use Scenario: Shielding RS-232 or CAN FD debug ports on factory-floor HMIs from maintenance technician ESD events. IC Role / Device Role / Timing Role: Low-leakage (≤20 μA) transient protector on bidirectional serial lines operating at 3.3 V or 5 V. Use Value: Eliminates need for series resistors or ferrites, reducing BOM count while sustaining >100,000 ESD strikes per line per lifetime. | Use Scenario: Protecting USB micro-B ports on bedside vital sign monitors handling frequent cable insertion/removal in clinical environments. IC Role / Device Role / Timing Role: First-stage ESD clamp on patient-connected equipment, meeting IEC 60601-1-2 4th edition immunity requirements. Use Value: Ensures uninterrupted operation during ±30 kV air discharge events without resetting MCU or corrupting sensor data streams. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| GSOT05-E3-18 | Higher VRWM (5 V), lower capacitance (260–350 pF), same SOT-23 package and BiAs architecture. | Better suited for 5 V logic or higher-speed interfaces where lower capacitance reduces signal distortion. | Select GSOT05-E3-18 when protecting 5 V tolerant lines or when sub-350 pF capacitance is required for >1 Gbps signaling. |
| VGSOT04 | Successor family with identical VRWM (4 V), improved PPP (480 W), tighter VC distribution, and extended AEC-Q101 coverage. | Designed for new designs requiring longer product lifecycle beyond January 2025 EOL date of GSOTxx series. | Choose VGSOT04 for production ramp after Q1 2025 or when enhanced surge margin and long-term supply assurance are mandatory. |
Compared with GSOT04-E3-18, GSOT05-E3-18 offers higher DC blocking voltage and lower parasitic capacitance for 5 V systems, while VGSOT04 provides extended availability, higher surge rating, and updated qualification - making it the strategic replacement for new designs targeting post-2025 deployment.
Availability
GSOT04-E3-18 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive infotainment data lines, and industrial HMI serial port hardening requiring stable component supply and documented ESD performance.
Supply support for GSOT04-E3-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and protection devices for automotive, industrial, and computing markets.
The GSOTxx series belongs to Vishay's dedicated ESD protection portfolio, engineered specifically for high-speed data line hardening with BiAs-mode architecture to balance clamping performance and signal fidelity in compact SOT-23 form factor.
FAQ
What is the maximum clamping voltage of GSOT04-E3-18 during an ESD event?
The GSOT04-E3-18 clamps to a maximum of 14.3 V at 30 A peak pulse current (IPPM) per IEC 61000-4-5 8/20 μs waveform. At lower currents (1 A), clamping is ≤9 V. This value ensures downstream 3.3 V ICs remain within absolute maximum ratings during worst-case transients. The BiAs-mode design yields lower forward clamping (≤4.5 V @ 30 A), critical for protecting receiver inputs.
Does GSOT04-E3-18 support automotive-grade qualification?
Yes - GSOT04-E3-18 is available in AEC-Q101-qualified versions denoted by the 'H' prefix (e.g., GSOT04-HE3-18). These variants undergo stress testing per AEC-Q101 including HTGB, AC-H3TRB, and ESD HBM (>8 kV), making them suitable for automotive infotainment, body control, and ADAS subsystems. Standard GSOT04-E3-18 is not AEC-Q101 qualified.
How does the BiAs-MODE architecture of GSOT04-E3-18 improve signal integrity?
BiAs-MODE enables asymmetric clamping: forward conduction (pin 3 → pin 1) clamps near ground (≤4.5 V @ 30 A), preserving low-voltage logic thresholds, while reverse conduction (pin 1 → pin 3) clamps higher (≤14.3 V @ 30 A) to handle positive surges. This prevents false triggering on bidirectional data lines like USB D+/D− and maintains timing margins without adding series impedance.
What is the capacitance of GSOT04-E3-18 at 2 V reverse bias, and why does it matter?
GSOT04-E3-18 exhibits 200 pF typical capacitance at 2 V reverse bias and 1 MHz. This value directly impacts signal rise time and eye opening in USB 2.0 (480 Mbps) applications: lower capacitance minimizes RC filtering and jitter. At 0 V bias, capacitance rises to 310–450 pF - hence operating bias point must be considered during high-speed layout.
Is GSOT04-E3-18 still in active production, and what is its end-of-life status?
GSOT04-E3-18 is scheduled for end-of-life in January 2025 per Vishay document 85807 (Rev. 2.9, Feb 2025). The recommended alternative is the VGSOTxx family, which offers pin-compatible replacements with enhanced specifications. Aetrix Electronics maintains active inventory and supports last-time buy planning, cross-reference validation, and transition support for GSOT04-E3-18 customers.
GSOT04-E3-18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Type:
- Zener
- Unidirectional Channels:
- 1
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 4V (Max)
- Voltage - Breakdown (Min):
- 5V
- Voltage - Clamping (Max) @ Ipp:
- 14.3V
- Current - Peak Pulse (10/1000µs):
- 30A (8/20µs)
- Power - Peak Pulse:
- 429W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 310pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
GSOT04-E3-18 FAQ
1.How can I place an order for GSOT04-E3-18 through Aetrix?
Please submit a Request for Quotation (RFQ) for GSOT04-E3-18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GSOT04-E3-18 reliable?
The price and inventory of GSOT04-E3-18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GSOT04-E3-18 is usually 5 days.
3.What payment methods are accepted for GSOT04-E3-18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GSOT04-E3-18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GSOT04-E3-18?
GSOT04-E3-18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GSOT04-E3-18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GSOT04-E3-18?
For technical support, including GSOT04-E3-18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GSOT04-E3-18 requirements.
6.How does Aetrix verify that GSOT04-E3-18 is sourced from the original manufacturer or authorized distributors?
All GSOT04-E3-18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GSOT04-E3-18 meets industry standards.
7.What is the process for return or replacement of GSOT04-E3-18?
All GSOT04-E3-18 units undergo pre-shipment inspection (PSI). If there is an issue with GSOT04-E3-18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GSOT04-E3-18 part is unused and in its original packaging.
Return procedure for GSOT04-E3-18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
GSOT04-E3-18 Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

