Vishay General Semiconductor - Diodes Division GSOT24C-HG3-18
- Part No.:
- GSOT24C-HG3-18
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
GSOT24C-HG3-18.pdf
- Description:
- TVS DIODE 24VWM 47VC SOT23
- Quantity:
- Payment:

- Shipping:

Inventory:5,154
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
GSOT24C-HG3-18 from Vishay Semiconductors is a two-line bidirectional asymmetrical ESD protection diode in SOT-23 package, rated for ±30 kV IEC 61000-4-2 contact/air discharge, 24 V reverse stand-off voltage (VRWM), and 5 A peak pulse current (IPPM). It protects high-speed data lines such as USB 2.0 or RS-485 interfaces against transient overvoltage events.
For engineers reviewing the GSOT24C-HG3-18 datasheet, GSOT24C-HG3-18 pinout, GSOT24C-HG3-18 application, or GSOT24C-HG3-18 equivalent, this device supports BiAs-mode (two-line ground-referenced) and BiSy-mode (single-line symmetrical) configurations, with verified clamping performance at 41 V (IPP = 5 A) and low 33–40 pF capacitance at 1 MHz for signal integrity preservation.
Technical Context
The GSOT24C-HG3-18 implements BiAs-MODE for dual-line protection: pins 1 and 2 connect to protected signal lines, pin 3 to ground, enabling independent clamping of positive transients (via reverse breakdown) and negative transients (via forward conduction). Its asymmetrical clamping behavior delivers 34–41 V reverse clamping and ≤1.4 V forward clamping at 5 A.
In BiSy-MODE (pin 3 unconnected), it functions as a single-line bidirectional protector with 24.5 V VRWM and 40–48 V clamping at 5 A, leveraging matched internal diodes for symmetrical response. Both modes comply with AEC-Q101 Class H3B (>8 kV HBM) and operate across –55 °C to +150 °C junction temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD immunity | ±30 kV contact & air discharge per IEC 61000-4-2 - meets industrial and automotive ESD robustness requirements without external shielding. |
| Reverse stand-off voltage (VRWM) | 24 V - ensures no leakage or conduction during normal 24 V system operation, suitable for 24 V CAN, RS-485, or sensor bus lines. |
| Peak pulse current (IPPM) | 5 A per line (IEC 61000-4-5, 8/20 μs) - sustains surge events typical in factory automation and motor control environments. |
| Clamping voltage (VC) | 41 V max at IPP = 5 A - limits transient voltage to safe levels for downstream 3.3 V/5 V logic or transceivers connected via series impedance. |
| Capacitance (CD) | 33–40 pF at 0 V, 1 MHz - low enough to avoid signal degradation on 10–40 Mbps data lines like PROFIBUS or Modbus RTU. |
| Operating temperature | –55 °C to +150 °C - qualified for under-hood automotive, industrial PLC, and power supply monitoring applications. |
| AEC-Q101 qualification | Class H3B (>8 kV HBM) - validated for automotive electronics where reliability under electrostatic stress is mission-critical. |
Pinout & Package
SOT-23 package (JEDEC TO-236AB), 3-pin surface-mount, 2.8 × 2.35 × 1.15 mm body, e3 Sn plating, MSL Level 1, peak reflow ≤260 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Line 1 anode / cathode | Connects to first protected signal line (L1); forms one half of BiAs protection path to ground (pin 3). |
| Pin 2 | Line 2 anode / cathode | Connects to second protected signal line (L2); forms second BiAs path to ground (pin 3); interchangeable with pin 1 in BiSy mode. |
| Pin 3 | Ground reference | Must be connected to system ground in BiAs mode; left floating in BiSy mode to enable symmetrical clamping between pins 1 and 2. |
Key Features
| Feature | Design Value |
|---|---|
| Two-line ESD protection | Simultaneous protection of differential or parallel signal pairs (e.g., RS-485 A/B, USB D+/D−) with shared ground return. |
| Bidirectional asymmetrical (BiAs) clamping | Enables low forward-voltage clamping (~1.4 V) for negative transients and controlled reverse clamping (41 V @ 5 A) for positives - preserves signal DC bias while limiting overshoot. |
| Low dynamic capacitance | 33–40 pF at 0 V enables use on 10–40 Mbps buses without measurable rise-time degradation or bit error rate increase. |
| AEC-Q101 qualified | Validated for automotive-grade reliability including temperature cycling, humidity bias, and mechanical shock - suitable for ADAS sensor interfaces and body control modules. |
| SOT-23 footprint compatibility | Standard 3-pin SOT-23 layout allows drop-in replacement in existing PCB designs without layout revision or solder mask changes. |
Applications
| Industrial RS-485 Network Node | Automotive CAN FD Transceiver Interface |
|---|---|
Use Scenario: Protecting RS-485 transceivers in factory floor PLCs exposed to ESD from operator touch and inductive switching noise. IC Role / Device Role / Timing Role: Two-line asymmetrical ESD clamp placed directly at connector entry point, shunting transients to chassis ground before reaching MAX13487 or SN65HVD7x ICs. Use Value: Maintains 24 V common-mode tolerance while limiting clamped voltage to ≤41 V, preventing latch-up or damage to 5 V transceiver I/O cells. |
Use Scenario: Safeguarding CAN FD physical layer in engine control units where 24 V battery-supplied nodes face load dump and ESD coupling. IC Role / Device Role / Timing Role: BiAs-mode protection on CAN_H/CAN_L lines referenced to vehicle chassis ground, operating alongside TCAN1042 or NXP TJA1044. Use Value: Withstands ±30 kV ESD and clamps 5 A surges to <41 V, ensuring CAN FD bit timing integrity up to 5 Mbps without added signal delay or jitter. |
| Smart Sensor Signal Conditioning Module | Building Automation BACnet MS/TP Bus |
Use Scenario: Shielding analog/digital sensor outputs (e.g., 4–20 mA loop-powered pressure sensors) from field-installation ESD and cable-induced transients. IC Role / Device Role / Timing Role: Dual-line protection on sensor's power and data lines, grounded to local PCB ground plane with minimal trace inductance. Use Value: 24 V VRWM matches standard industrial supply rails; 1 μA IR at 24 V prevents loading of precision current loops or ADC reference paths. |
Use Scenario: Securing BACnet MS/TP twisted-pair bus nodes in HVAC controllers subjected to building-wide grounding differences and maintenance ESD. IC Role / Device Role / Timing Role: BiSy-mode configuration (pin 3 open) used on differential pair to provide symmetrical clamping without ground reference dependency. Use Value: 33–40 pF capacitance avoids distortion of 76.8 kbps Manchester-encoded signals; 24.5 V VRWM accommodates 24 V nominal bus voltage with margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| VGSOT24C-G3-18 | Direct successor in Vishay's active portfolio; identical SOT-23 package, same 24 V VRWM and ±30 kV ESD rating, but updated process for improved consistency in VBR (27–33 V) and lower CD variation. | Pin-to-pin compatible with GSOT24C-HG3-18; supports identical BiAs/BiSy modes and operates across same temperature range. | Select for new designs requiring long-term supply continuity beyond January 2025 end-of-life date of GSOT24C-HG3-18. |
| SMAJ24AHE3/A | Single-line 24 V TVS diode in DO-214AC package; 30 kW peak power, 13.9 A IPPM, but higher 100 pF capacitance and no dual-line integration. | Requires two devices plus routing for dual-line protection; unsuitable for space-constrained layouts or high-speed buses due to capacitance. | Use only when discrete placement flexibility is available and signal speed <1 Mbps; not a functional or footprint replacement. |
Compared with GSOT24C-HG3-18, VGSOT24C-G3-18 offers guaranteed lifecycle support and tighter parameter distribution, while SMAJ24AHE3/A delivers higher surge capacity at the cost of board area, parasitic capacitance, and design complexity - making the original GSOT24C-HG3-18 optimal for compact, high-integrity dual-line protection where EOL timing permits.
Availability
GSOT24C-HG3-18 is available at Aetrix Electronics and suitable for industrial automation, automotive subsystems, and building management systems requiring stable component supply through its end-of-life date in January 2025.
Supply support for GSOT24C-HG3-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and passive components for automotive, industrial, and computing markets.
The GSOTxxC family was designed specifically for robust, space-efficient ESD protection of high-speed data and power lines in harsh environments, emphasizing low clamping voltage, AEC-Q101 qualification, and dual-mode (BiAs/BiSy) flexibility.
FAQ
What is the maximum operating temperature for GSOT24C-HG3-18?
The GSOT24C-HG3-18 has a junction temperature range of –55 °C to +150 °C, validated per AEC-Q101 stress testing. This allows deployment in under-hood automotive locations, industrial motor drives, and outdoor equipment enclosures without thermal derating up to the upper limit.
Does GSOT24C-HG3-18 support both BiAs and BiSy protection modes?
Yes, GSOT24C-HG3-18 supports both modes: BiAs-mode (pins 1 and 2 to signal lines, pin 3 to ground) for two-line asymmetric clamping, and BiSy-mode (pin 3 unconnected, pins 1 and 2 across a single differential pair) for symmetrical bipolar protection - both defined in the official Vishay GSOT03C–GSOT36C datasheet.
What is the clamping voltage of GSOT24C-HG3-18 at 5 A peak pulse current?
In BiAs-mode (pin 1 or 2 to pin 3), the reverse clamping voltage of GSOT24C-HG3-18 is 41 V maximum at IPP = 5 A (IEC 61000-4-5, 8/20 μs waveform), measured per the absolute maximum ratings table for GSOT24C in Document Number 85824 Rev. 3.0.
Is GSOT24C-HG3-18 RoHS-compliant and lead-free?
Yes, GSOT24C-HG3-18 carries the "HG3" suffix indicating RoHS-compliant, lead-free construction with e3 matte tin plating, conforming to JEDEC J-STD-020 moisture sensitivity level 1 and peak reflow temperature of 260 °C.
What is the capacitance of GSOT24C-HG3-18 at 1 MHz and 0 V bias?
The typical capacitance of GSOT24C-HG3-18 is 65–80 pF at VR = 0 V and f = 1 MHz, as specified in the ELECTRICAL CHARACTERISTICS table for GSOT24C (Tamb = 25 °C), making it suitable for data lines up to 40 Mbps without significant signal attenuation.
GSOT24C-HG3-18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 27V
- Voltage - Clamping (Max) @ Ipp:
- 47V
- Current - Peak Pulse (10/1000µs):
- 5A (8/20µs)
- Power - Peak Pulse:
- 235W
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 65pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
GSOT24C-HG3-18 FAQ
1.How can I place an order for GSOT24C-HG3-18 through Aetrix?
Please submit a Request for Quotation (RFQ) for GSOT24C-HG3-18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GSOT24C-HG3-18 reliable?
The price and inventory of GSOT24C-HG3-18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GSOT24C-HG3-18 is usually 5 days.
3.What payment methods are accepted for GSOT24C-HG3-18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GSOT24C-HG3-18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GSOT24C-HG3-18?
GSOT24C-HG3-18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GSOT24C-HG3-18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GSOT24C-HG3-18?
For technical support, including GSOT24C-HG3-18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GSOT24C-HG3-18 requirements.
6.How does Aetrix verify that GSOT24C-HG3-18 is sourced from the original manufacturer or authorized distributors?
All GSOT24C-HG3-18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GSOT24C-HG3-18 meets industry standards.
7.What is the process for return or replacement of GSOT24C-HG3-18?
All GSOT24C-HG3-18 units undergo pre-shipment inspection (PSI). If there is an issue with GSOT24C-HG3-18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GSOT24C-HG3-18 part is unused and in its original packaging.
Return procedure for GSOT24C-HG3-18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
GSOT24C-HG3-18 Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

