Vishay General Semiconductor - Diodes Division GSOT36C-HG3-18
- Part No.:
- GSOT36C-HG3-18
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
GSOT36C-HG3-18.pdf
- Description:
- TVS DIODE 36VWM 71VC SOT23
- Quantity:
- Payment:

- Shipping:

Inventory:6,946
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
GSOT36C-HG3-18 from Vishay Semiconductors is a two-line bidirectional asymmetrical ESD protection diode in SOT-23 package, rated for ±30 kV IEC 61000-4-2 contact/air discharge, 36 V reverse stand-off voltage (VRWM), and 3.5 A peak pulse current (IPPM). It protects high-speed data lines such as USB 2.0 or CAN FD interfaces against transient overvoltage.
For engineers reviewing the GSOT36C-HG3-18 datasheet, GSOT36C-HG3-18 pinout, GSOT36C-HG3-18 application, or GSOT36C-HG3-18 equivalent, key selection criteria include clamping voltage at 3.5 A (≤71 V), low 26–33 pF capacitance at 0 V bias, AEC-Q101 qualification, RoHS-compliant green e3 Sn plating, and SOT-23 footprint compatibility with space-constrained automotive and industrial PCBs.
Technical Context
The GSOT36C-HG3-18 implements BiAs-MODE (Bidirectional Asymmetrical) protection: pins 1 and 2 connect to protected signal lines, pin 3 to ground, enabling independent clamping of positive transients via reverse breakdown (VBR = 39–47 V) and negative transients via forward conduction (VF ≤ 1.3 V at 3.5 A). Its dual-diode architecture delivers asymmetric clamping-critical for mixed-voltage interfaces where ground-referenced negative excursions must be tightly controlled.
When configured in BiSy-MODE (pin 1 to line, pin 2 to ground, pin 3 open), it operates as a single-line symmetrical protector with VRWM = 36.5 V and clamping symmetry defined by matched VBR + VF summation. Both modes maintain full IEC 61000-4-2/4-5 compliance and operate across –55 °C to +150 °C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD immunity | ±30 kV contact & air discharge per IEC 61000-4-2 - meets highest system-level ESD robustness requirements without external shielding. |
| Reverse stand-off voltage | 36 V (VRWM) - supports 3.3 V, 5 V, 12 V, and 24 V logic/data rails while blocking normal operating voltages. |
| Peak pulse current | 3.5 A (IPPM, 8/20 μs) - handles severe surge events per IEC 61000-4-5 with 248 W peak power capability. |
| Clamping voltage | ≤71 V at 3.5 A (VC) - limits downstream IC stress during worst-case transients, preserving 36 V-rated interface components. |
| Capacitance | 26–33 pF at 0 V (CD) - enables use on USB 2.0 (480 Mbps), CAN FD (5 Mbps), and RS-485 links without signal integrity degradation. |
| Operating temperature | –55 °C to +150 °C (TJ) - qualified for under-hood automotive, industrial motor control, and outdoor telecom applications. |
| AEC-Q101 qualified | Yes - validated for automotive electronics per stress test standard, including HBM >8 kV (Class H3B). |
Pinout & Package
SOT-23 package (JEDEC TO-236AB), 3-pin, surface-mount, e3 matte tin (Sn) plating, MSL Level 1, 8.8 mg weight, UL 94 V-0 molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Anode of D1 / Cathode of D2 | Connects to first protected signal line (L1); forms one half of BiAs dual-path protection network. |
| Pin 2 | Anode of D2 / Cathode of D1 | Connects to second protected signal line (L2); enables simultaneous protection of differential or parallel data lines. |
| Pin 3 | Cathode of D1 & D2 / Ground reference | Must be connected to system ground; provides common return path for clamped transient current in BiAs mode. |
Key Features
| Feature | Design Value |
|---|---|
| BiAs-MODE dual-line protection | Enables simultaneous, independent ESD suppression on two signal lines referenced to common ground-reducing component count vs. discrete diodes. |
| Low clamping capacitance | 26–33 pF at 0 V allows integration into high-speed digital interfaces without bandwidth limitation or signal reflection. |
| AEC-Q101 qualification | Validated for automotive-grade reliability including temperature cycling, mechanical shock, and HBM ESD stress-supports Tier-1 supply chain requirements. |
| e3 Sn plating | Lead-free, RoHS-compliant matte tin termination ensures solderability and intermetallic compatibility with Pb-free reflow profiles. |
| MSL Level 1 rating | Unlimited floor life before reflow-eliminates baking requirements and simplifies manufacturing logistics. |
Applications
| Automotive Infotainment Data Lines | Industrial RS-485 Communication Ports |
|---|---|
Use Scenario: Protecting USB 2.0, CAN FD, or LIN bus traces in head units, telematics modules, and ADAS sensors exposed to cable discharge events. IC Role / Device Role / Timing Role: Two-line ESD clamp placed directly at connector entry point to shunt transients before reaching PHY or MCU I/O pins. Use Value: Maintains signal integrity up to 5 Mbps (CAN FD) with <33 pF loading while surviving ±30 kV ESD strikes-reducing field failure rates in vehicle assembly and service environments. | Use Scenario: Safeguarding RS-485 transceivers in factory automation PLCs, motor drives, and building management systems interfacing with long cables. IC Role / Device Role / Timing Role: Bidirectional asymmetrical clamp on differential A/B lines, referenced to local chassis ground to suppress common-mode surges. Use Value: Limits clamping voltage to ≤71 V at 3.5 A, ensuring transceiver survival during 4 kV EFT bursts and lightning-induced surges on unshielded wiring runs. |
| Medical Patient Monitoring Interfaces | Consumer USB-C Port Protection |
Use Scenario: Shielding isolated analog front-end data lines (e.g., ECG, SpO₂) connected to patient-worn sensors from electrostatic discharge during handling or cable coupling. IC Role / Device Role / Timing Role: Low-leakage (IR ≤1 μA at 36 V) ESD suppressor placed between sensor harness and isolation barrier to preserve signal DC accuracy. Use Value: Delivers ±30 kV ESD immunity without adding measurable offset or noise-critical for sub-mV biomedical signal fidelity and IEC 60601-1-2 compliance. | Use Scenario: Front-end protection for USB-C receptacles in laptops, docking stations, and peripherals subject to frequent hot-plug and user-handling ESD events. IC Role / Device Role / Timing Role: Dual-line clamp on CC and SBU lines, or BiSy configuration on VBUS detection circuitry to prevent latch-up in power delivery controllers. Use Value: Combines 36 V VRWM with 26 pF capacitance to protect both high-speed data and power negotiation signals without degrading USB 2.0 eye diagram or PD handshake timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| VGSOT36C-HG3-18 | Direct successor family; identical SOT-23 footprint, same VRWM (36 V), improved thermal resistance and lower leakage (IR ≤0.5 μA). | End-of-life replacement with extended lifecycle support; compatible with existing GSOT36C-HG3-18 layouts and test fixtures. | Select when long-term supply continuity and enhanced reliability for new designs are required. |
| SMF36A-T | Single-line unidirectional TVS; 36 V VRWM, 400 W peak power, but lacks dual-line capability and BiAs functionality. | Requires two devices for dual-line protection; higher board area and BOM cost; no inherent asymmetry for mixed-rail interfaces. | Choose only for cost-sensitive, single-line applications where BiAs operation is unnecessary. |
Compared with GSOT36C-HG3-18, VGSOT36C-HG3-18 offers extended product lifetime and tighter leakage specs, while SMF36A-T requires duplication for dual-line coverage and cannot replicate BiAs clamping behavior-making GSOT36C-HG3-18 uniquely suited for compact, high-integrity two-signal protection.
Availability
GSOT36C-HG3-18 is available at Aetrix Electronics and suitable for automotive infotainment, industrial RS-485 networks, and medical patient monitoring systems requiring stable component supply through January 2025 end-of-life date.
Supply support for GSOT36C-HG3-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and passive components for automotive, industrial, and computing markets.
The GSOTxxC series was designed specifically for board-level ESD protection of high-speed data interfaces, emphasizing low capacitance, precise clamping, and AEC-Q101 qualification for harsh-environment deployment.
FAQ
What is the maximum operating temperature range for the GSOT36C-HG3-18?
The GSOT36C-HG3-18 has a junction temperature range of –55 °C to +150 °C, making it suitable for under-hood automotive applications, industrial motor drives, and outdoor telecom equipment where ambient temperatures exceed 105 °C. This rating is verified per AEC-Q101 stress testing and applies across its full electrical specification range.
Does the GSOT36C-HG3-18 support both BiAs-MODE and BiSy-MODE configurations?
Yes, the GSOT36C-HG3-18 supports both configurations: BiAs-MODE (pins 1 & 2 to signal lines, pin 3 to ground) for two-line asymmetrical protection, and BiSy-MODE (pin 1 to line, pin 2 to ground, pin 3 open) for single-line symmetrical clamping. Each mode uses distinct electrical characteristics-VRWM is 36 V in BiAs and 36.5 V in BiSy-as specified in the official Vishay datasheet revision 3.0.
What is the clamping voltage of the GSOT36C-HG3-18 at its rated peak pulse current?
At its rated peak pulse current of 3.5 A (8/20 μs waveform), the GSOT36C-HG3-18 exhibits a maximum reverse clamping voltage (VC) of 71 V when protecting two lines (pin 1–3 or pin 2–3), and 72 V in BiSy-MODE (pin 1–2). These values are measured per IEC 61000-4-5 and ensure downstream ICs rated for 36 V operation remain within safe voltage margins.
Is the GSOT36C-HG3-18 RoHS-compliant and lead-free?
Yes, the GSOT36C-HG3-18 carries the "HG3" suffix indicating RoHS-compliant, lead-free construction with e3 matte tin (Sn) plating. It meets JEDEC J-STD-020 moisture sensitivity level 1 and is qualified for Pb-free reflow soldering up to 260 °C peak temperature, as documented in Vishay's package data sheet 85824.
What is the typical capacitance of the GSOT36C-HG3-18 at zero bias voltage?
The GSOT36C-HG3-18 exhibits a typical capacitance of 26–33 pF at 0 V reverse bias and 1 MHz frequency, measured between each signal pin (1 or 2) and ground (pin 3). This low value enables reliable use on USB 2.0, CAN FD, and RS-485 links without compromising rise time or introducing impedance discontinuities.
GSOT36C-HG3-18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 36V (Max)
- Voltage - Breakdown (Min):
- 39V
- Voltage - Clamping (Max) @ Ipp:
- 71V
- Current - Peak Pulse (10/1000µs):
- 3.5A (8/20µs)
- Power - Peak Pulse:
- 248W
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 52pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
GSOT36C-HG3-18 FAQ
1.How can I place an order for GSOT36C-HG3-18 through Aetrix?
Please submit a Request for Quotation (RFQ) for GSOT36C-HG3-18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for GSOT36C-HG3-18 reliable?
The price and inventory of GSOT36C-HG3-18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GSOT36C-HG3-18 is usually 5 days.
3.What payment methods are accepted for GSOT36C-HG3-18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GSOT36C-HG3-18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for GSOT36C-HG3-18?
GSOT36C-HG3-18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your GSOT36C-HG3-18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for GSOT36C-HG3-18?
For technical support, including GSOT36C-HG3-18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GSOT36C-HG3-18 requirements.
6.How does Aetrix verify that GSOT36C-HG3-18 is sourced from the original manufacturer or authorized distributors?
All GSOT36C-HG3-18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GSOT36C-HG3-18 meets industry standards.
7.What is the process for return or replacement of GSOT36C-HG3-18?
All GSOT36C-HG3-18 units undergo pre-shipment inspection (PSI). If there is an issue with GSOT36C-HG3-18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The GSOT36C-HG3-18 part is unused and in its original packaging.
Return procedure for GSOT36C-HG3-18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
GSOT36C-HG3-18 Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

