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Home > Products > Integrated Circuits (ICs) > Logic > Latches

STMicroelectronics HCF4099M013TR

Name: HCF4099M013TR
Brand: STMicroelectronics
SKU: HCF4099M013TR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: HCF4099M013TR

Manufacturer:: STMicroelectronics

Category:: Latches

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: HCF4099M013TR.pdf

Description:: IC LATCH 8BIT ADDRESSABLE 16SOIC

Quantity:: RFQ Add To RFQ list

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Inventory:2,296

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Product details

Overview

HCF4099M013TR from STMicroelectronics is an 8-bit addressable latch IC with serial data input and active parallel output, master clear functionality, demultiplexer capability, and operation up to 20 V supply. It features symmetrical output characteristics, 100 nA max input leakage at 18 V, and is qualified for industrial temperature range (–55 °C to +125 °C). Used in digital control systems requiring selective bit storage and routing.

For engineers reviewing the HCF4099M013TR datasheet, HCF4099M013TR pinout, HCF4099M013TR application, or HCF4099M013TR equivalent, key selection criteria include addressable latch behavior, WRITE DISABLE-controlled write gating, RESET-synchronized clearing, and DC/AC performance across 3–20 V VDD.

Technical Context

The HCF4099M013TR implements a CMOS-based 8-bit storage register where individual bits are selected via 3-bit binary address (A0–A2) and written only when WRITE DISABLE is low. Data entry is inhibited when WRITE DISABLE is high, yet all Q0–Q7 outputs remain readable regardless of address or WRITE DISABLE state.

In demultiplexer mode (RESET high, WRITE DISABLE low), the addressed output follows the DATA input while unaddressed outputs are forced low. A synchronous master RESET clears all latched bits to logic "0" when both RESET and WRITE DISABLE are high.

Key Specifications

Parameter	Value and Actual Design Meaning
VDD Range	3 V to 20 V - supports wide-supply industrial and legacy 5/10/15 V logic systems
Input Leakage	±0.1 µA max at 18 V - ensures minimal loading on high-impedance address/data lines
Propagation Delay	50 ns min / 400 ns max (VDD = 5–15 V) - defines timing budget for address/data synchronization
Output Drive	±1.1 mA min at VDD = 5 V - sufficient to drive TTL loads or multiple CMOS inputs
Operating Temp	–55 °C to +125 °C - qualified for automotive under-hood and industrial control environments
Quiescent Current	0.04 µA typ at VDD = 5 V - enables ultra-low-power standby in battery-backed systems

Pinout & Package

Package: 16-pin SOIC (Small Outline Integrated Circuit), body width 3.9 mm, pitch 1.27 mm, JEDEC standard SO-16 footprint (PO13H).

Pin/Terminal	Circuit Role	Design Meaning
1, 15, 14, 13, 12, 11, 10, 9	Q0–Q7	Active-high parallel latch outputs; each reflects stored bit value or demux data when addressed
5, 6, 7	A0–A2	3-bit binary address inputs selecting one of eight latch positions or output channels
3	DATA	Serial input source for latch write or demux data path; sampled on WRITE DISABLE transition
2	RESET	Asynchronous master clear; forces all Q outputs low when high and WRITE DISABLE is also high
4	WRITE DISABLE	Write enable control: low permits data write to addressed bit; high freezes latch state
8	VSS	Negative supply reference (GND); required for CMOS bias and noise margin stability
16	VDD	Positive supply rail (3–20 V); powers internal logic and determines output voltage swing

Key Features

Feature	Design Value
Addressable latch architecture	Selectively updates one of eight bits without disturbing others - ideal for partial register writes
Dual-mode operation	Configurable as storage register (WRITE DISABLE gated) or 1-of-8 demultiplexer (RESET + WRITE DISABLE combo)
Wide VDD tolerance	3–20 V operation eliminates need for level-shifting in mixed-voltage systems
Guaranteed quiescent current test	100% tested at 20 V - ensures reliability in high-VDD industrial applications

Applications

Industrial PLC I/O Expansion

Legacy System Bus Interface

Use Scenario: Adding discrete output points to programmable logic controllers using minimal address/data lines.

IC Role / Device Role / Timing Role: Addressable latch providing isolated, software-selectable 8-bit parallel output staging.

Use Value: Reduces microcontroller GPIO count by 11 pins (3 address + 1 data + 1 WD + 1 RESET + 8 Q) versus discrete latches.

Use Scenario: Interfacing 8-bit microprocessors (e.g., Z80, 8085) to peripheral devices with shared address/data buses.

IC Role / Device Role / Timing Role: Latch holding decoded I/O port address to enable peripheral selection during bus cycles.

Use Value: Eliminates need for external address decoding logic; supports direct memory-mapped I/O with single-cycle setup.

LED Matrix Row Driver

Test Equipment Signal Routing

Use Scenario: Driving rows of multiplexed LED displays in industrial HMIs where brightness control requires stable current sources.

IC Role / Device Role / Timing Role: Demultiplexer routing PWM or enable signals to individual row drivers under microcontroller address control.

Use Value: Enables dynamic row selection without flicker; Q outputs sink up to 6.8 mA at 15 V - sufficient for direct LED drive.

Use Scenario: Automated test fixtures requiring configurable signal path switching between DUT pins and measurement instruments.

IC Role / Device Role / Timing Role: Programmable signal gate enabling or blocking test stimulus paths based on test step address.

Use Value: Provides deterministic, glitch-free path selection with sub-100 ns propagation delay - critical for timing-sensitive measurements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar addressable latch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
CD4099BE	Same function and pinout; wider package options (DIP-16), but not qualified to –55 °C and lacks 100% I_Q test at 20 V	Suitable for commercial-temp lab equipment; not recommended for extended-temperature industrial use	Prefer HCF4099M013TR where full military-grade temp range and guaranteed quiescent current are required
74HC573PW	Octal transparent latch with 3-state outputs; no address decoding or demux mode; different control logic (G and OE)	Used in bus-hold applications, not address-selective storage or demux functions	Only viable if system redesign allows removal of address decoding and accepts non-addressable latch behavior

Compared with CD4099BE and 74HC573PW, the HCF4099M013TR uniquely combines address-selective write, demultiplexer mode, and extended temperature qualification - making it irreplaceable in legacy-compatible, high-reliability embedded control designs.

Availability

HCF4099M013TR is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy system bus interface, and LED matrix row driver applications requiring stable component supply across long product lifecycles.

Supply support for HCF4099M013TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

The HCF4099B series belongs to ST's legacy B-series CMOS logic family, engineered specifically for robust, wide-supply operation in industrial control and retro-compatibility applications where reliability across extreme temperatures and voltages is essential.

FAQ

What is the maximum clock/data frequency supported by HCF4099M013TR?

The device does not operate on a clock signal; it is edge-triggered by WRITE DISABLE transitions and address changes. Maximum reliable operation depends on propagation delays: at VDD = 15 V, t_PLH/t_PHL is 50–100 ns, supporting effective toggle rates up to ~5 MHz in demux mode with proper pulse width margins (t_W ≥ 40 ns).

Can HCF4099M013TR drive LEDs directly?

Yes - each Q output can sink up to 6.8 mA at VDD = 15 V (I_OL = 6.8 mA min), sufficient for low-current indicator LEDs. For higher-brightness or multi-LED loads, external transistor drivers are recommended due to power dissipation limits (100 mW per output transistor).

Is RESET asynchronous or synchronous with WRITE DISABLE?

RESET is asynchronous: asserting RESET high (while WRITE DISABLE is also high) immediately forces all Q outputs low, independent of address or data timing. However, the reset action only completes when both RESET and WRITE DISABLE are simultaneously high - this dual-input requirement prevents accidental clearing during normal write operations.

Does HCF4099M013TR support 3.3 V logic systems?

No - the minimum recommended VDD is 3 V, but DC specifications (VIH/VIL, VOH/VOL, drive strength) are only guaranteed down to VDD = 5 V per JEDEC JESD13B. At 3.3 V, output levels and noise margins fall outside specification; use only at VDD ≥ 5 V for compliant operation.

HCF4099M013TR Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: 4000B

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: D-Type, Addressable

Circuit:: 1:8

Output Type:: Standard

Voltage - Supply:: 3V ~ 20V

Independent Circuits:: 1

Delay Time - Propagation:: 50ns

Current - Output High, Low:: 6.8mA, 6.8mA

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

HCF4099M013TR FAQ

1.How can I place an order for HCF4099M013TR through Aetrix?

Please submit a Request for Quotation (RFQ) for HCF4099M013TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for HCF4099M013TR reliable?

The price and inventory of HCF4099M013TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HCF4099M013TR is usually 5 days.

3.What payment methods are accepted for HCF4099M013TR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HCF4099M013TR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for HCF4099M013TR?

HCF4099M013TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your HCF4099M013TR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for HCF4099M013TR?

For technical support, including HCF4099M013TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HCF4099M013TR requirements.

6.How does Aetrix verify that HCF4099M013TR is sourced from the original manufacturer or authorized distributors?

All HCF4099M013TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HCF4099M013TR meets industry standards.

7.What is the process for return or replacement of HCF4099M013TR?

All HCF4099M013TR units undergo pre-shipment inspection (PSI). If there is an issue with HCF4099M013TR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The HCF4099M013TR part is unused and in its original packaging.

Return procedure for HCF4099M013TR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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