Infineon Technologies IGLT65R035D2ATMA1

Overview

IGLT65R035D2ATMA1 from Infineon is a 650 V, 35 mΩ enhancement-mode GaN HEMT in PG-HDSOP-16 package with Kelvin source and integrated gate diode. It delivers 97 A pulsed drain current, 7.7 nC total gate charge, and zero reverse recovery charge - enabling high-frequency totem-pole PFC and LLC resonant converters in datacenter SMPS. Its 0.81 °C/W junction-to-case thermal resistance supports high-power-density designs.

For engineers reviewing the IGLT65R035D2ATMA1 datasheet, IGLT65R035D2ATMA1 pinout, IGLT65R035D2ATMA1 application, or IGLT65R035D2ATMA1 equivalent, key selection criteria include its 650 V blocking rating, 35 mΩ R_DS(on) at 13 A/25°C, Kelvin-source layout for gate drive stability, ultra-low Q_oss (142 pF time-related), and absence of reverse-recovery charge in bidirectional conduction.

Technical Context

This CoolGaN™ G5 transistor uses lateral GaN-on-Si technology with a dedicated Kelvin source terminal (Pin 10) to eliminate source inductance impact on gate control loop stability. Its gate threshold voltage (1.2 V typ) and −10 V to +25 V gate-source voltage rating support robust drive under transient conditions.

The device features zero Q_rr, 57 nC output charge at 400 V, and 200 V/ns dv/dt immunity - enabling hard-switched topologies up to 1 MHz without snubbers. Thermal design leverages its 0.81 °C/W R_thJC and heatslug-connected drain (Pins 1–8) for direct PCB copper thermal spreading.

Key Specifications

Pinout & Package

PG-HDSOP-16 package with exposed heatslug (drain-connected), integrated gate diode, and dedicated Kelvin source terminal for stable gate control. Pin 10 is isolated Kelvin source; Pins 11–16 are main source terminals; Pins 1–8 form the thermal drain pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage GaN transistor applications.

Compared with GS66508T and TPH3205WS, IGLT65R035D2ATMA1 offers superior high-frequency stability via Kelvin source, lower conduction loss at 13 A, and guaranteed zero Q_rr - making it optimal for >500 kHz totem-pole and LLC designs demanding minimal EMI and maximum power density.

Availability

IGLT65R035D2ATMA1 is available at Aetrix Electronics and suitable for server PSUs, datacenter LLC converters, industrial DC-DC bricks, and EV onboard chargers requiring stable component supply and long-term lifecycle support.

Supply support for IGLT65R035D2ATMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs and discrete devices.

This part belongs to the CoolGaN™ G5 product line, engineered specifically for high-efficiency, high-frequency power conversion in 650 V applications - targeting next-generation SMPS architectures where Si and SiC face switching loss or layout limitations.

FAQ

What gate driver voltage range is recommended for reliable operation?

Infineon specifies −10 V to +25 V continuous and −25 V to +25 V pulsed gate-source voltage. For stable switching, use −3 V to +6 V turn-off and +5.5 V to +6 V turn-on with a 3.3 Ω series gate resistor. This avoids exceeding the 19 mA average gate current limit while maintaining <1 ns propagation delay mismatch between parallel devices.

How does the Kelvin source connection affect PCB layout?

The Kelvin source (Pin 10) must connect directly to the gate driver's source reference node - not to the main source copper pour. A separate 0.2 mm wide trace, ≤5 mm long, minimizes inductance. Routing this trace over an unbroken ground plane prevents coupling into the gate loop, which is essential to avoid oscillation at >1 MHz switching frequencies.

Can IGLT65R035D2ATMA1 replace silicon MOSFETs in existing 650 V designs without layout changes?

No - the PG-HDSOP-16 footprint and Kelvin source requirement mandate PCB redesign. The drain pad (Pins 1–8) occupies 12.5 × 12.5 mm, and Pin 10 must be isolated from main source routing. Existing TO-247 or D²PAK layouts cannot accommodate the thermal and signal integrity requirements of this GaN device.

What is the maximum allowable case temperature during continuous operation?

The datasheet specifies 150°C maximum junction temperature, but the 0.81 °C/W R_thJC and 94 °C/W R_thJA (on minimal PCB) mean case temperature must stay ≤105°C to maintain 80% lifetime derating. At 48 A continuous drain current, thermal simulation shows 92°C case temp on 6 cm² copper - confirming suitability for forced-air-cooled 3 kW systems.