International Test Instruments Corporation IR2135JPBF

Overview

IR2135JPBF from Infineon Technologies is a high-voltage, high-speed 3-phase bridge driver IC with independent high-side and low-side gate drive channels, rated for up to 600 V offset voltage, ±200 mA / +420 mA output current, 750 ns / 700 ns typical turn-on/turn-off propagation delay, and 250 ns matched deadtime. It integrates an analog current-sense amplifier and over-current shutdown for motor inverter stages in industrial AC drives.

For engineers reviewing the IR2135JPBF datasheet, IR2135JPBF pinout, IR2135JPBF application, or IR2135JPBF equivalent, key selection criteria include floating channel dV/dt immunity, bootstrap-compatible 10–20 V gate supply range, 2.5 V logic compatibility, undervoltage lockout per channel, and fault-clear functionality via FLT-CLR pin.

Technical Context

The IR2135JPBF employs proprietary HVIC (High-Voltage IC) monolithic technology to integrate three independent half-bridge drivers with matched propagation delays (750 ns on / 700 ns off), enabling precise synchronous PWM control in 3-phase inverters. Its floating channels support N-channel MOSFET or IGBT high-side switching up to 600 V VS offset.

An integrated operational amplifier provides real-time analog current feedback via external sense resistor, while dedicated ITRIP input triggers simultaneous shutdown of all six outputs upon over-current detection. Fault status is reported via open-drain FAULT pin, cleared only by asserting FLT-CLR - ensuring fail-safe operation in safety-critical motor control.

Key Specifications

Pinout & Package

IR2135JPBF is housed in a 28-lead SOIC (wide-body) package with gull-wing leads, optimized for thermal dissipation and creepage in high-voltage motor drive PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-phase gate driver applications.

Compared with IR2135JPBF, IR2133JPBF offers identical timing and logic but reduced UVLO hysteresis and lower voltage rating, while IRS2330JPbF trades analog current feedback for higher voltage capability and integrated bootstrap diodes - making IR2135JPBF optimal for cost-sensitive, medium-voltage industrial inverters requiring embedded current monitoring.

Availability

IR2135JPBF is available at Aetrix Electronics and suitable for industrial AC motor drives, brushless DC controllers, solar inverters, and uninterruptible power supplies requiring stable component supply across long production lifecycles.

Supply support for IR2135JPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs, with leadership in high-voltage gate driver innovation since the 1990s.

The IR21xx family was designed specifically for ruggedized 3-phase inverter gate driving in industrial motor control, emphasizing dV/dt immunity, integrated protection, and analog feedback integration - distinguishing it from generic half-bridge drivers.

FAQ

What is the maximum allowable dV/dt at the VS pins for reliable operation?

The IR2135JPBF is specified for 50 V/ns dV/dt immunity at the VS pins under all operating conditions. This value is validated per datasheet test condition PD60107 revX and ensures no false turn-on occurs during fast high-side switching transients in 600 V bus systems, provided layout minimizes parasitic inductance in the VS return path.

Can the CAO output drive an ADC input directly without external buffering?

Yes - CAO delivers rail-to-rail output (0–5.4 V) with ±20 mV low-level accuracy and 7 mA source capability, enabling direct connection to 12-bit SAR ADCs with ≥10 kΩ input impedance. The 70 dB CMRR and 50 dB PSRR ensure measurement integrity even with shared VCC supply and noisy motor current paths.

How does the ITRIP blanking time interact with PWM frequency and deadtime?

The fixed 400 ns ITRIP blanking window begins at each rising edge of HIN/LIN and disables over-current detection during switch transition. At 20 kHz PWM (50 µs period), blanking occupies only 0.8% of cycle time and does not interfere with deadtime enforcement, which is handled independently by internal logic with 250 ns precision.

Is the FLT-CLR pin required to be actively driven, or can it be tied high?

FLT-CLR must be actively pulled low to clear a latched fault; tying it high leaves FAULT asserted indefinitely. The pin has 200 µA "high" bias current and requires ≤0.8 V to register logic low. A microcontroller GPIO or open-collector driver is recommended - passive pull-up alone cannot reset the latch.