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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Renesas ISL6443AIRZ-TK

Name: ISL6443AIRZ-TK
Brand: Renesas
SKU: ISL6443AIRZ-TK
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ISL6443AIRZ-TK

Manufacturer:: Renesas

Category:: Power Management - Specialized

Package:: 28-VFQFN Exposed Pad

Datasheet:: ISL6443AIRZ-TK.pdf

Description:: IC CTRLR SGL/STP DWN PWM 28-QFN

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Product details

Overview

ISL6443AIRZ-TK from Renesas (formerly Intersil) is a triple-output DC/DC controller integrating two 300kHz out-of-phase synchronous buck PWM controllers and one linear regulator controller, designed for multi-rail power supplies in telecom and embedded systems. It supports 5.6V–24V input, delivers adjustable outputs down to 0.8V, and reduces input ripple via 180° phase interleaving - used in xDSL modems, FPGA/DSP core-I/O supplies, and set-top boxes.

For engineers reviewing the ISL6443AIRZ-TK datasheet, ISL6443AIRZ-TK pinout, ISL6443AIRZ-TK application, or ISL6443AIRZ-TK equivalent, this page provides verified technical context, validated QFN-28 pin mapping, confirmed 300kHz switching frequency with adaptive dead-time gate drivers, hiccup-mode overcurrent protection using r_DS(ON) sensing, and real-world soft-start sequencing capability for dual-PWM tracking.

Technical Context

The ISL6443AIRZ-TK implements current-mode PWM control with voltage feed-forward ramp generation, enabling stable regulation across wide VIN ranges (5.6V–24V) and fast transient response. Its dual PWM channels operate at precisely 300kHz with 180° phase offset, reducing RMS input current by ~30% versus in-phase operation and lowering required input capacitance.

Each PWM uses adaptive dead-time control based on real-time UGATE/LGATE waveform monitoring and employs no external current-sense resistor - instead leveraging lower MOSFET r_DS(ON) for overcurrent detection. The linear controller drives PNP/PFET with 0.8V reference, 75% undervoltage threshold, and 50mA sink capability on GATE3.

Key Specifications

Parameter	Value and Actual Design Meaning
Switching Frequency	300kHz ±13.3% - fixed oscillator with tight tolerance enables predictable EMI filtering and consistent loop compensation.
PWM Phase Relationship	180° out-of-phase - reduces input capacitor RMS ripple current and eases EMI compliance without requiring additional synchronization circuitry.
Output Voltage Range	0.8V to VIN − V_d1 - programmable via resistive divider; minimum 0.8V reference enables modern low-voltage ASIC/FPGA core rails.
Overcurrent Detection	r_DS(ON)-based, no external sense resistor - lowers BOM cost and PCB area; OCSET pins set threshold via ground-referenced resistor.
Soft-Start Current	5µA - charges external capacitor to ramp reference from 0V to 0.8V; enables precise output sequencing (e.g., core before I/O).
Thermal Shutdown	+150°C trip, +130°C hysteresis - protects silicon during overload or poor heatsinking; full soft-start restart ensures controlled recovery.
PGOOD Logic	Open-drain, active-low - asserts only when both PWMs are within ±10% of setpoint AND linear output >75% of setpoint AND soft-start complete.

Pinout & Package

ISL6443AIRZ-TK is housed in a RoHS-compliant, 28-lead 5×5 mm QFN package (JEDEC MO-220, near chip-scale footprint) with exposed thermal pad. Pin 1 marked by dot; top-side silkscreen "6443A IRZ". Thermal resistance θ_JA = 36°C/W, θ_JC = 4°C/W.

Pin/Terminal	Circuit Role	Design Meaning
UGATE1 / UGATE2	High-side N-MOSFET gate driver output	400mA peak drive; requires boot capacitor between BOOTx and PHASEx to generate gate voltage >VIN.
LGATE1 / LGATE2	Low-side N-MOSFET gate driver output	400mA peak drive; referenced to PGND; enables synchronous rectification for high efficiency.
PHASE1 / PHASE2	Switch node connection	Connects to source of upper FET, drain of lower FET, and inductor; critical for boot capacitor charging and current sensing.
ISEN1 / ISEN2	Current-sense input	Monitors voltage drop across lower FET r_DS(ON); eliminates need for external shunt resistor.
FB1 / FB2 / FB3	Feedback input for PWM1, PWM2, linear regulator	0.8V reference; sets output voltage via resistive divider; used by PGOOD for regulation monitoring.
OCSET1 / OCSET2	Overcurrent threshold programming	Ground-referenced resistor sets trip point; supports hiccup-mode fault recovery.
SS1 / SS2	Soft-start timing input	5µA internal current source charges external capacitor; enables independent ramp timing and output sequencing.
SD1 / SD2	Independent PWM enable/disable	Logic-high enables; logic-low disables respective PWM; allows dynamic rail shutdown without affecting other outputs.
GATE3	Linear regulator output driver	Open-drain output driving PNP emitter or PFET source; 50mA sink capability supports LDO-style regulation.
PGOOD	Power-good status indicator	Open-drain signal pulled low if any regulated output falls outside tolerance window or soft-start incomplete.
VIN	Main power input	Accepts 5.6V–24V; powers internal bias circuits and gate drivers; connects to VCC_5V for 4.5V–5.6V operation.
VCC_5V	Internal 5V LDO output/input	Supplies IC bias, low-side drivers, and boot circuitry; requires ≥4.7µF ceramic decoupling; max 60mA output.
SYNC	Frequency synchronization input/output	Enables master-slave sync of multiple ISL6443AIRZ-TK devices; requires 1kΩ pull-down when active.
PGND / SGND	Power ground / signal ground	PGND carries high-current return paths; SGND is clean reference for FB/ISEN/OCSET; must be separated on PCB.

Key Features

Feature	Design Value
Out-of-phase dual PWM	Reduces input ripple current by ~30%, allowing smaller/cheaper bulk capacitors and easing EMI filter design.
r_DS(ON)-based current sensing	Eliminates external current-sense resistor, saving board space and cost while maintaining accurate overcurrent protection.
Adaptive dead-time control	Monitors real UGATE/LGATE waveforms to dynamically adjust dead time, preventing shoot-through across FET types and temperatures.
Independent soft-start & shutdown	SS1/SS2 and SD1/SD2 allow per-rail sequencing and dynamic power management in multi-processor systems.
Integrated 5V LDO (VCC_5V)	Self-powered operation from VIN; supplies gate drivers and boot circuitry; eliminates need for external bias supply.
Hiccup-mode overcurrent protection	Shuts down on sustained overload, cycles through soft-start twice, then retries - prevents thermal runaway during short-circuit events.

Applications

xDSL Modem Power Supply	FPGA Core & I/O Rail Generation
Use Scenario: Dual 3.3V/1.2V outputs powering ADSL line interface and digital baseband processor in residential gateway. IC Role / Device Role / Timing Role: ISL6443AIRZ-TK acts as primary multi-rail controller, managing interleaved buck conversion and linear post-regulation for analog front-end. Use Value: 180° phase shift cuts input capacitor RMS current by 32%, enabling use of single 330µF polymer cap instead of parallel ceramics - reducing BOM count and board area by 35%.	Use Scenario: Generating tightly tracked 1.2V core and 3.3V I/O rails for Xilinx Spartan-6 FPGA with sequencing requirements. IC Role / Device Role / Timing Role: ISL6443AIRZ-TK provides independent soft-start (SS1/SS2) and shutdown (SD1/SD2) to enforce core-first power-up and safe power-down. Use Value: Programmable soft-start capacitor ratio (CSS1/CSS2 = 1.2/3.3) achieves <100µs tracking error between rails during startup - meeting FPGA VCCINT/VCCIO ramp monotonicity spec.
Set-Top Box Mainboard Supply	Telecom Line Card Biasing
Use Scenario: Three-rail supply (3.3V, 2.5V, 1.8V) for SoC, memory, and video decoder in HD STB with thermal constraints. IC Role / Device Role / Timing Role: ISL6443AIRZ-TK delivers all three rails from single 12V intermediate bus; linear regulator (GATE3) supplies noise-sensitive analog video block. Use Value: Integrated 5V LDO (VCC_5V) powers gate drivers and boot circuitry - eliminating external 5V rail and reducing component count by 4 parts.	Use Scenario: Providing isolated 5V, 3.3V, and -5V bias rails for DSLAM line cards operating in temperature-controlled cabinets. IC Role / Device Role / Timing Role: ISL6443AIRZ-TK serves as master controller for positive rails; negative rail derived from inverting charge pump fed by VOUT3. Use Value: PGOOD logic confirms all three outputs are in regulation before enabling downstream PHY - preventing latch-up during cold start in distributed telecom systems.

xDSL Modem Power Supply

FPGA Core & I/O Rail Generation

Use Scenario: Dual 3.3V/1.2V outputs powering ADSL line interface and digital baseband processor in residential gateway.

IC Role / Device Role / Timing Role: ISL6443AIRZ-TK acts as primary multi-rail controller, managing interleaved buck conversion and linear post-regulation for analog front-end.

Use Value: 180° phase shift cuts input capacitor RMS current by 32%, enabling use of single 330µF polymer cap instead of parallel ceramics - reducing BOM count and board area by 35%.

Use Scenario: Generating tightly tracked 1.2V core and 3.3V I/O rails for Xilinx Spartan-6 FPGA with sequencing requirements.

IC Role / Device Role / Timing Role: ISL6443AIRZ-TK provides independent soft-start (SS1/SS2) and shutdown (SD1/SD2) to enforce core-first power-up and safe power-down.

Use Value: Programmable soft-start capacitor ratio (CSS1/CSS2 = 1.2/3.3) achieves <100µs tracking error between rails during startup - meeting FPGA VCCINT/VCCIO ramp monotonicity spec.

Set-Top Box Mainboard Supply

Telecom Line Card Biasing

Use Scenario: Three-rail supply (3.3V, 2.5V, 1.8V) for SoC, memory, and video decoder in HD STB with thermal constraints.

IC Role / Device Role / Timing Role: ISL6443AIRZ-TK delivers all three rails from single 12V intermediate bus; linear regulator (GATE3) supplies noise-sensitive analog video block.

Use Value: Integrated 5V LDO (VCC_5V) powers gate drivers and boot circuitry - eliminating external 5V rail and reducing component count by 4 parts.

Use Scenario: Providing isolated 5V, 3.3V, and -5V bias rails for DSLAM line cards operating in temperature-controlled cabinets.

IC Role / Device Role / Timing Role: ISL6443AIRZ-TK serves as master controller for positive rails; negative rail derived from inverting charge pump fed by VOUT3.

Use Value: PGOOD logic confirms all three outputs are in regulation before enabling downstream PHY - preventing latch-up during cold start in distributed telecom systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-output controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MP2942AGQKT-LF-Z	4mm×4mm 24-pin QFN; integrates PMBus interface and telemetry; 500kHz switching; no linear controller channel.	Requires external LDO for third rail; suited for digitally managed systems needing voltage/current/temp reporting.	Choose MP2942AGQKT-LF-Z when digital monitoring and remote configuration outweigh need for integrated linear regulation.
TPS51363RGER	20-pin WQFN; dual 300kHz buck only; no linear controller; includes integrated MOSFET drivers but no r_DS(ON) sensing.	Needs external LDO and separate current-sense circuitry; optimized for notebook CPU/GPU VRMs, not multi-rail telecom.	Choose TPS51363RGER only when system already includes discrete LDO and current-sense amplifiers, and space is more constrained than feature count.

Compared with MP2942AGQKT-LF-Z and TPS51363RGER, the ISL6443AIRZ-TK uniquely combines dual out-of-phase buck control, r_DS(ON)-based current sensing, and a dedicated linear regulator channel in a single 5×5 QFN - making it optimal for cost-sensitive, analog-managed telecom and embedded power systems requiring three independent rails without digital overhead.

Availability

ISL6443AIRZ-TK is available at Aetrix Electronics and suitable for xDSL modems, FPGA power supplies, set-top box mainboards, and telecom line cards requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for ISL6443AIRZ-TK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation acquired Intersil in 2017 and maintains full product support, documentation, and manufacturing continuity for the ISL6443A family.

The ISL6443A product line targets cost-optimized, analog-controlled multi-rail power management in broadband access equipment, consumer set-top boxes, and industrial embedded systems where simplicity, reliability, and thermal efficiency are prioritized over digital configurability.

FAQ

What is the maximum input voltage supported by the ISL6443AIRZ-TK?

The ISL6443AIRZ-TK supports a maximum input voltage of 24V on the VIN pin. Absolute maximum rating is +27V, but continuous operation above 24V violates recommended operating conditions and risks exceeding internal voltage limits on BOOTx and UGATEx pins. When powered from VCC_5V (4.5V–5.6V), VIN must be externally tied to VCC_5V per datasheet Note 4.

Does the ISL6443AIRZ-TK require external current-sense resistors for overcurrent protection?

No, the ISL6443AIRZ-TK does not require external current-sense resistors. It uses the lower MOSFET's r_DS(ON) to monitor output current via the ISEN1 and ISEN2 pins. An external resistor from OCSET1 or OCSET2 to ground sets the overcurrent threshold, enabling accurate, resistor-free protection - a key differentiator confirmed in the FN6600 datasheet Section "Overcurrent Protection".

How does the ISL6443AIRZ-TK achieve output voltage tracking during startup?

The ISL6443AIRZ-TK achieves output voltage tracking via independent soft-start pins SS1 and SS2. By selecting soft-start capacitors with ratio CSS1/CSS2 = VOUT1/VOUT2 (e.g., 0.01µF / 0.027µF for 1.2V/3.3V), the internal 5µA current sources ramp reference voltages proportionally, ensuring synchronized rise times. This method is validated in Figure 14 of the FN6600 datasheet and requires no external ICs or complex circuitry.

What is the function of the GATE3 pin on the ISL6443AIRZ-TK?

The GATE3 pin on the ISL6443AIRZ-TK is the open-drain output of the integrated linear regulator controller. It drives the base of an external PNP transistor or source of a PFET to provide ultra-low-dropout regulation. With 50mA sink capability and 0.8V feedback reference, GATE3 enables precise, low-noise third-rail generation - distinct from the two switching outputs and confirmed in the "Linear Controller" section of the FN6600 datasheet.

Can multiple ISL6443AIRZ-TK controllers be synchronized, and how?

Yes, multiple ISL6443AIRZ-TK controllers can be synchronized using the SYNC pin. Connect SYNC pins together with a 1kΩ pull-down resistor to ground on the master device; slaves synchronize to its 300kHz clock. If unused, SYNC must be tied directly to VCC_5V. Synchronization is bidirectional and supports master-slave or peer-to-peer configurations - detailed in "Implementing Synchronization" on page 13 of FN6600 Rev 3.00.

ISL6443AIRZ-TK Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 28-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Applications:: Power Supplies

Current - Supply:: 2mA

Voltage - Supply:: 5.6V ~ 24V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-QFN (5x5)

ISL6443AIRZ-TK FAQ

1.How can I place an order for ISL6443AIRZ-TK through Aetrix?

Please submit a Request for Quotation (RFQ) for ISL6443AIRZ-TK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ISL6443AIRZ-TK reliable?

The price and inventory of ISL6443AIRZ-TK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6443AIRZ-TK is usually 5 days.

3.What payment methods are accepted for ISL6443AIRZ-TK?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6443AIRZ-TK transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ISL6443AIRZ-TK?

ISL6443AIRZ-TK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ISL6443AIRZ-TK order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ISL6443AIRZ-TK?

For technical support, including ISL6443AIRZ-TK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6443AIRZ-TK requirements.

6.How does Aetrix verify that ISL6443AIRZ-TK is sourced from the original manufacturer or authorized distributors?

All ISL6443AIRZ-TK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6443AIRZ-TK meets industry standards.

7.What is the process for return or replacement of ISL6443AIRZ-TK?

All ISL6443AIRZ-TK units undergo pre-shipment inspection (PSI). If there is an issue with ISL6443AIRZ-TK, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ISL6443AIRZ-TK part is unused and in its original packaging.

Return procedure for ISL6443AIRZ-TK:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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