Renesas ISL6537ACRZ

Overview

ISL6537ACRZ from Renesas (formerly Intersil) is an ACPI-compliant dual-channel DDR/DDR2 memory power controller integrating five regulated outputs: synchronous buck PWM for VDDQ (0.8V–2.5V), 3A sink-source linear regulator for DDR VTT, PWM for GMCH core, LDO for CPU/GMCH VTT termination, and LDO for DAC. It delivers ±2% output regulation over temperature and supports glitch-free S0/S1/S3 state transitions in ATX-based desktop and graphics card systems.

For engineers reviewing the ISL6537ACRZ datasheet, ISL6537ACRZ pinout, ISL6537ACRZ application, or ISL6537ACRZ equivalent, key selection considerations include its 250kHz phase-shifted dual-PWM architecture, integrated adaptive shoot-through protection, VDDQ/2 buffered VREF output, 0°C to +70°C operating range, and Pb-free 28-lead 6×6 QFN package with exposed thermal pad.

Technical Context

The ISL6537ACRZ implements two independent 250kHz voltage-mode PWM controllers - one fully integrated (VDDQ) with UGATE/LGATE drivers and adaptive shoot-through protection, the other (GMCH core) requiring external MOSFET drivers via PWM4/DRIVE2/DRIVE3. Both use a shared 0.800V precision reference and are phase-shifted 180° to reduce input ripple.

Its five-output architecture includes: (1) VDDQ buck regulator with OCSET-based overcurrent protection using r_DS(ON) sensing; (2) integrated 3A VTT linear regulator with DDR_VTTSNS feedback and VREF_OUT buffer; (3) GMCH core PWM with FB4/COMP4 loop; (4) CPU/GMCH VTT LDO controlled by DRIVE2/FB2; and (5) DAC LDO controlled by DRIVE3/FB3 - all coordinated under ACPI sleep-state logic (S3#/S5#).

Key Specifications

Pinout & Package

ISL6537ACRZ is housed in a RoHS-compliant, Pb-free 28-lead 6×6 mm QFN package (PKG DWG L28.6x6) with exposed thermal pad for enhanced thermal dissipation. The package requires solder reflow per JEDEC J-STD-020 Pb-free profile.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail DDR memory power controller applications.

Compared with ISL6537CRZ and RT8802AGQW, the ISL6537ACRZ uniquely combines five-rail integration, VREF_OUT buffering, VIDPGD status signaling, and hardware-enforced 180° PWM phase shift - making it the only option qualified for ACPI-compliant dual-channel DDR2 memory systems with GMCH and CPU termination requirements.

Availability

ISL6537ACRZ is available at Aetrix Electronics and suitable for desktop motherboards, graphics cards, ASIC I/O power, embedded DDR2 interfaces, and industrial computing platforms requiring stable component supply across extended production lifecycles.

Supply support for ISL6537ACRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics acquired Intersil in 2017 and maintains full technical and manufacturing continuity for legacy Intersil power management ICs including the ISL6537A family.

The ISL6537A product line was designed specifically for ACPI-compliant DDR/DDR2 memory power systems in ATX-based PCs and graphics cards - emphasizing hardware-controlled state transitions, multi-rail integration, and thermal resilience in dense PCB layouts.

FAQ

What is the function of the VIDPGD pin on the ISL6537ACRZ?

The VIDPGD pin on the ISL6537ACRZ is an open-drain status output that indicates whether the VTT_GMCH/CPU linear regulator is within specification. It transitions to high-impedance only during S0/S1/S2 states when VTT_GMCH/CPU voltage is within ±2% of 0.8 V; otherwise, it remains logic-low. This signal allows system logic to verify termination rail readiness before enabling the processor or GPU - a critical check in ACPI-compliant boot sequences. The ISL6537ACRZ uses this pin to provide hardware-level confirmation without software polling.

Does the ISL6537ACRZ support DDR3 or DDR4 memory standards?

No, the ISL6537ACRZ is explicitly designed for DDR and DDR2 memory systems, as confirmed by its datasheet title ("ACPI Regulator/Controller for Dual Channel DDR Memory Systems"), supported VDDQ range (down to 0.8 V, targeting 1.8 V DDR2 and 2.5 V DDR), and VTT_DDR output set to VDDQ/2. It does not meet DDR3 (1.5 V VDDQ, VTT = 0.75 V) or DDR4 (1.2 V VDDQ, VTT = 0.6 V) voltage and timing requirements. For DDR3/DDR4, Renesas offers later-generation controllers such as the ISL6538 or RT8802A. The ISL6537ACRZ remains optimal for legacy DDR/DDR2 platforms.

How does the ISL6537ACRZ implement overcurrent protection on the VDDQ rail?

The ISL6537ACRZ implements VDDQ overcurrent protection using an r_DS(ON)-based sensing method: an internal 20 µA current source (IOCSET) flows through an external ROCSET resistor, generating a voltage referenced to P12V; when the voltage drop across the upper MOSFET (V_PHASE – V_BOOT) exceeds this ROCSET voltage, the controller triggers hiccup-mode soft-start restart. This eliminates the need for a lossy current-sense resistor while maintaining accuracy across temperature. The ISL6537ACRZ datasheet provides Equation 1 (I_PEAK = IOCSET × ROCSET / r_DS(ON)) to calculate trip threshold - a design feature unique to this controller's efficiency-focused architecture.

Can the ISL6537ACRZ be used in a single-channel DDR system?

Yes, the ISL6537ACRZ is fully compatible with single-channel DDR/DDR2 systems. Its architecture supports up to 4 DIMMs across dual channels, but all five regulated outputs - VDDQ, VTT_DDR, VREF_OUT, VGMCH, and VTT_GMCH/CPU - remain functional in single-channel configurations. Designers simply connect the unused channel's DIMM VTT traces to the ISL6537ACRZ's DDR_VTT pins and omit GMCH-related components if not needed. The ISL6537ACRZ's ACPI state machine, soft-start sequencing, and protection features operate identically regardless of channel count - making it scalable from entry-level single-channel to high-end dual-channel implementations.

What is the purpose of the VREF_IN capacitor in the ISL6537ACRZ application circuit?

The capacitor connected between VREF_IN and ground (CSS) in the ISL6537ACRZ application circuit controls the soft-start ramp rate of the VTT_DDR regulator during S3→S0 transitions. It forms an RC time constant with the internal VTT divider impedance (RU||RL = 1.25 kΩ), ensuring the VTT_DDR output rises smoothly to 50% of VDDQ without exceeding the LDO's current limit. Equation 2 in the ISL6537ACRZ datasheet (CSS > CVTTOUT × VDDQ / (10 × 2A × RU||RL)) defines the minimum value. This capacitor is essential for preventing VTT overshoot and inrush current - a design requirement unique to the ISL6537ACRZ's floating-VTT architecture during sleep-state recovery.