Renesas ISL6537CR

Overview

ISL6537CR from Renesas Electronics (formerly Intersil) is an ACPI-compliant dual-channel DDR memory power controller integrating a 250kHz synchronous buck PWM controller for VDDQ, a 3A sink-source linear regulator for DDR VTT (VDDQ/2), two LDO controllers for GMCH core and GMCH/CPU VTT termination, and a buffered VREF_OUT reference. It delivers ±2% output regulation over line, load, and temperature in 0°C to +70°C ambient, targeting ATX-powered desktop and graphics card memory subsystems.

For engineers reviewing the ISL6537CR datasheet, ISL6537CR pinout, ISL6537CR application, or ISL6537CR equivalent, key selection considerations include its 28-pin 6×6 QFN package, SLP_S3/S5 sleep-state control interface, integrated adaptive shoot-through protection, VDDQ overcurrent hiccup-mode response, and VIDPGD status signaling for GMCH/CPU VTT regulation compliance.

Technical Context

The ISL6537CR implements voltage-mode PWM control with a fixed 250kHz oscillator and 8.2ms typical soft-start interval. Its VDDQ regulation loop uses a precision 0.8V internal reference, DC gain of 80dB, and 15MHz gain-bandwidth product to achieve fast transient response and ±2% static tolerance.

All four regulated outputs-VDDQ (buck), DDR VTT (integrated linear), GMCH core (LDO), and GMCH/CPU VTT (LDO)-feature independent undervoltage monitoring; VDDQ adds overvoltage and overcurrent protection via OCSET pin and PHASE sensing, while thermal shutdown activates at +140°C junction temperature.

Key Specifications

Pinout & Package

ISL6537CR is housed in a thermally enhanced 28-lead 6×6 mm QFN package with exposed ground paddle. The package supports Pb-free reflow per IPC/JEDEC J-STD-020 and provides low θJC = 5°C/W for efficient heat dissipation in dense memory power layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power controller applications.

Compared with ISL6537CR, ISL6537CRZ offers identical performance with RoHS-compliant packaging, while RT8120BZQW provides higher-frequency DDR3 support but omits two integrated LDO controllers-making it unsuitable for complete dual-channel DDR2 memory power solutions without additional components.

Availability

ISL6537CR is available at Aetrix Electronics and suitable for desktop motherboards, graphics cards, ASIC memory interfaces, and embedded processor I/O supplies requiring stable component supply and long-term lifecycle continuity.

Supply support for ISL6537CR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics acquired Intersil in 2017 and maintains full technical and supply chain support for legacy Intersil power management ICs including the ISL6537 family.

The ISL6537CR belongs to Intersil's ACPI-compliant memory power controller product line, designed specifically for cost-sensitive, high-reliability DDR/DDR2 memory subsystems in ATX-based computing platforms.

FAQ

What is the primary function of the ISL6537CR in a DDR memory system?

The ISL6537CR serves as a complete ACPI-compliant power controller for dual-channel DDR/DDR2 memory systems. It integrates a synchronous buck PWM controller for VDDQ, a 3A sink-source linear regulator for DDR VTT (VDDQ/2), two LDO controllers for GMCH core and GMCH/CPU VTT termination, and a buffered VREF_OUT reference. The ISL6537CR manages all four regulated rails with coordinated sleep-state sequencing and comprehensive fault protection, eliminating the need for multiple discrete regulators in ATX-based platforms.

Does the ISL6537CR support both DDR and DDR2 memory voltage requirements?

Yes, the ISL6537CR supports both DDR and DDR2 memory specifications. Its VDDQ output is user-adjustable down to 0.8V using an external resistor divider on the FB pin, covering the 2.5V DDR and 1.8V DDR2 nominal VDDQ ranges. The ±2% regulation tolerance over line, load, and temperature, combined with fast transient response and precise 0.8V internal reference, ensures compliance with JEDEC timing and voltage margin requirements for both memory generations.

How does the ISL6537CR implement overcurrent protection for the VDDQ buck converter?

The ISL6537CR implements VDDQ overcurrent protection using MOSFET rDS(ON) sensing via the OCSET pin. An internal 20µA current source develops a voltage across an external ROCSET resistor, which is compared to the voltage drop across the upper MOSFET's rDS(ON) sensed at the PHASE pin. When the sensed voltage exceeds the ROCSET threshold, the ISL6537CR initiates hiccup-mode soft-start cycling. This method avoids external sense resistors, improves efficiency, and allows programmable trip points based on MOSFET selection and thermal conditions.

What is the role of the VIDPGD pin on the ISL6537CR?

The VIDPGD pin on the ISL6537CR is an open-drain logic output that indicates the regulation status of the GMCH/CPU VTT rail. During S0/S1/S2 states, VIDPGD is pulled high-impedance when VTT_GMCH/CPU is within specification (0.725V–0.74V rising, 0.70V–0.715V falling); it is forced low in all other states or if the rail falls out of regulation. This signal provides system-level confirmation of VTT readiness for memory initialization and is used by chipset logic to validate power-good sequencing before enabling memory access.

Can the ISL6537CR operate without a 12V supply in all power states?

No-the ISL6537CR requires the P12V supply only during S0/S1 operation to power the VTT linear regulator and DRIVEx gate drivers. In S3/S4/S5 sleep states, P12V is not required; the device operates solely from the 5VSBY bias rail, drawing less than 1mA in S5 mode. This enables low-power retention of VDDQ regulation while disabling non-essential functions, aligning with ACPI-defined power state behavior for memory subsystems.