Renesas ISL6537CR-T

Overview

ISL6537CR-T from Renesas (formerly Intersil) is an ACPI-compliant dual-channel DDR memory power controller integrating a 250kHz synchronous buck PWM controller for VDDQ, a ±3A sink-source linear regulator for DDR VTT, two LDO controllers for GMCH core and GMCH/CPU VTT, and a buffered VREF_OUT at 0.8V. It supports S0/S1/S3 states in ATX-powered desktop and graphics systems with ±2% output regulation over temperature.

For engineers reviewing the ISL6537CR-T datasheet, ISL6537CR-T pinout, ISL6537CR-T application, or ISL6537CR-T equivalent, key selection considerations include its 28-pin 6×6 QFN package, integrated adaptive shoot-through protection, VDDQ overcurrent hiccup mode via OCSET resistor, VIDPGD fault signaling, and precise VDDQ/2 tracking for DDR/DDR2 termination compliance.

Technical Context

The ISL6537CR-T implements voltage-mode PWM control with 250kHz fixed-frequency operation and fast transient response for the VDDQ buck converter, while using internal error amplifiers (80dB DC gain, 15MHz GBWP) for all four regulated outputs. Its soft-start sequencing is digitally controlled across five stages-VDDQ_DDR and upper VGMCH first, then lower VGMCH, VTT_GMCH/CPU, and finally VTT_DDR-with VREF_IN capacitor timing the VTT_DDR ramp.

ACPI state transitions are managed via S3# and S5# inputs, enabling glitch-free regulator enable/disable during S0↔S3↔S5 transitions. Fault handling includes per-rail undervoltage monitoring, VDDQ/VTT_DDR overvoltage shutdown (requiring S5# toggle to clear), and a fault counter that triggers full shutdown after 4 faults on cold start or 5 faults during runtime.

Key Specifications

Pinout & Package

ISL6537CR-T is housed in a thermally enhanced 28-lead 6×6 mm QFN package with exposed ground paddle. The package supports Pb-free reflow per IPC/JEDEC J-STD-020 and requires low-inductance grounding of the paddle to PCB ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power controller applications.

Compared with ISL6537IRZ-T, ISL6537CR-T provides greater solder process flexibility due to its Pb-free plus anneal construction, while RT8120AGQW lacks integrated VTT regulation and ACPI S3/S5 sequencing-making ISL6537CR-T uniquely suited for cost-sensitive, space-constrained DDR2 memory power designs requiring full ACPI compliance.

Availability

ISL6537CR-T is available at Aetrix Electronics and suitable for desktop motherboard design, graphics card development, and embedded graphics controller power systems requiring stable component supply, long-lifecycle availability, and RoHS-compliant sourcing.

Supply support for ISL6537CR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics acquired Intersil in 2017 and maintains full technical and supply chain continuity for legacy Intersil power management ICs including the ISL6537 family.

The ISL6537 product line was designed specifically for ACPI-compliant DDR/DDR2 memory power delivery in desktop, graphics, and embedded computing platforms-emphasizing integration, thermal robustness, and seamless sleep-state transitions.

FAQ

What is the function of the OCSET pin on the ISL6537CR-T?

The OCSET pin on the ISL6537CR-T connects to an external resistor (ROCSET) that, together with the internal 20µA current source and the upper MOSFET's rDS(ON), sets the VDDQ overcurrent trip threshold. When the voltage across the upper MOSFET exceeds the voltage across ROCSET, the ISL6537CR-T initiates hiccup-mode soft-start recovery. This eliminates the need for a lossy current-sense resistor while maintaining accurate, temperature-compensated overcurrent protection for the VDDQ rail.

How does the ISL6537CR-T manage VTT regulation during S3 sleep state?

During S3 state, the ISL6537CR-T disables the internal DDR VTT regulator and internally shorts the VTT reference to the DDR_VTT output pins, allowing the VTT rail to float. This prevents unnecessary current draw while maintaining termination voltage integrity across memory and MCH I/O pins. The VTT rail voltage decays only due to leakage, and the ISL6537CR-T resumes full regulation upon S3→S0 transition using the VREF_IN capacitor to control the VTT_DDR ramp rate-ensuring glitch-free wake-up.

Can the ISL6537CR-T support DDR2 memory systems?

Yes, the ISL6537CR-T explicitly supports DDR2 memory systems. Its VDDQ output is adjustable down to 0.8V to meet DDR2 VDDQ specifications, and its VTT regulator delivers ±3A bidirectional current with precise VDDQ/2 tracking via VREF_OUT. The datasheet confirms compatibility with "up to 4 DIMM dual channel DDR/DDR2 Memory systems," and its 250kHz PWM frequency, ±2% regulation, and ACPI S3/S5 sequencing align with DDR2 platform power requirements.

What is the role of the VIDPGD pin on the ISL6537CR-T?

The VIDPGD pin on the ISL6537CR-T is an open-drain logic output that indicates whether the VTT_GMCH/CPU rail is within regulation during S0/S1/S2 states. It pulls low when VTT_GMCH/CPU falls outside its ±2% window (0.70V–0.74V), providing a hardware-level power-good signal for system BIOS or PMU validation. In all other states-including S3 and S4/S5-the pin remains low, making it a dedicated fault indicator rather than a general-purpose status flag.

Does the ISL6537CR-T require external components for VDDQ soft-start?

No, the ISL6537CR-T implements fully integrated digital soft-start for the VDDQ buck regulator. Upon power-up or S3→S0 transition, it clamps the COMP pin reference to a rising internal voltage ramp, generating increasing-width PHASE pulses that charge the output capacitor in a controlled manner. The typical soft-start interval is 8.2ms, and no external timing capacitors or resistors are needed-though loop compensation components (RC network between COMP and FB) remain required for stability.