Microchip Technology KSZ8692XPB

Overview

KSZ8692XPB from Micrel Inc. is a 400-pin PBGA System-on-Chip (SoC) integrating a 250 MHz ARM922T processor, dual 10/100 Mbps Ethernet MACs with MII interface, PCI 2.3 host/guest interface supporting one external master, and dual USB 2.0 ports with integrated PHY - designed for residential gateways and VoIP systems requiring embedded networking and communications control.

For engineers reviewing the KSZ8692XPB datasheet, KSZ8692XPB pinout, KSZ8692XPB application, or KSZ8692XPB equivalent, key selection considerations include its single-PCI-master configuration (vs. three in KSZ8692MPB), absence of SDIO support, DDR controller with 32-bit bus and 200 MHz clock, 1.3V core voltage, and glueless NAND/FLASH/SRAM interface with automatic ADDR[1] address mapping for byte/half-word flexibility.

Technical Context

The KSZ8692XPB implements an AMBA AHB 2.0 bus operating up to 166 MHz, with the ARM922T as sole AHB master configuring DDR, Ethernet, PCI, and USB peripherals. Its AHB connects to an APB bridge managing UARTs, timers, GPIO, I²C, SPI, and I²S - all accessible via dedicated DMA channels.

It supports Little-Endian mode, configurable MMU for Linux/WinCE, and power management features including CPU/AMBA clock scaling, Wake-on-LAN, and DDR/PCI power-down. The DDR controller uses a dedicated PLL (up to 200 MHz), provides JEDEC-compliant SSTL_2 I/Os, and integrates two JESD82-1 differential clock drivers for glueless DDR interface.

Key Specifications

Pinout & Package

KSZ8692XPB is housed in a 400-pin Plastic Ball Grid Array (PBGA) package with 0.8 mm pitch, compliant with JEDEC MO-251. Pinout information is defined in Figure 20 (Ball Grid Array Map) and Table on page 41 of Rev. 4.0 datasheet. Key functional groups include DDR data/address/control balls, MII signals for both Ethernet ports, PCI AD/CBE# lines, USB DP/DM pairs, and dedicated reset/power management pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar embedded networking controller applications.

Compared with KSZ8692MPB, KSZ8692XPB removes SDIO and limits PCI to one master - reducing cost and complexity for fixed-function gateways. Against LPC3250FET208, KSZ8692XPB delivers superior networking integration (dual MAC, PCI, USB 2.0) but omits multimedia peripherals, making it more focused for communications infrastructure.

Availability

KSZ8692XPB is available at Aetrix Electronics and suitable for residential gateways, VoIP adapters, and industrial control gateways requiring stable component supply across long-lifecycle embedded deployments.

Supply support for KSZ8692XPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Micrel Inc. was a U.S.-based semiconductor company specializing in analog, power management, and communications ICs before its acquisition by Microchip Technology in 2015.

The KSZ8692XPB belongs to Micrel's KSZ8692 family of highly integrated networking SoCs, designed specifically to consolidate Ethernet, PCI, USB, DDR, and ARM processing into a single chip for cost-sensitive, high-bandwidth residential and industrial communications equipment.

FAQ

What is the maximum DDR data rate supported by the KSZ8692XPB?

The KSZ8692XPB DDR controller operates at up to 200 MHz clock frequency, delivering a 400 MT/s data rate on its 32-bit bus. It supports JEDEC-compliant SSTL_2 I/Os and includes two integrated differential clock drivers meeting JESD82-1 specification - enabling a complete glueless DDR interface without external clock generation circuitry. This allows efficient access to up to 128 MB of DDR SDRAM using 12-column and 14-row addressing.

Does the KSZ8692XPB support SDIO or microSD card interfaces?

No, the KSZ8692XPB does not support SDIO or microSD card interfaces. That functionality is exclusive to the KSZ8692MPB variant, as explicitly stated in the datasheet's ordering information and block diagrams. The KSZ8692XPB omits the SDIO/SD host controller block shown only in Figure 3 (MPB) and absent in Figure 4 (XPB). Designers requiring removable storage must select KSZ8692MPB or implement external SDIO bridge logic.

How many external PCI masters does the KSZ8692XPB support?

The KSZ8692XPB supports exactly one external PCI master, as confirmed in the "PCI Interface" section and ordering table footnote "(2) Support for one PCI Master. No SDIO." This differs from the KSZ8692MPB, which supports three external masters via its integrated PCI arbiter. The single-master limitation simplifies arbitration logic and reduces silicon area, aligning with the XPB's target in cost-constrained, fixed-role gateway applications.

What power supply voltages are required for the KSZ8692XPB?

The KSZ8692XPB requires three distinct supply rails: 1.3 V for the core logic (ARM922T and internal buses), 3.3 V for general-purpose I/O including MII, USB, UART, and GPIO, and 2.5 V or 2.6 V for the DDR memory interface. These values are specified in the "Operating Voltage" section and reinforced in the "Electrical Characteristics" table. Proper sequencing - particularly powering the 1.3 V core before 3.3 V I/O - is mandatory per the "Power-up Strapping Options" section to ensure reliable boot and operation.

Is the KSZ8692XPB pin-compatible with the KSZ8692MPB?

Yes, the KSZ8692XPB is pin-compatible with the KSZ8692MPB: both use identical 400-pin PBGA packages with matching ball map, signal assignments, and mechanical footprint. This allows drop-in replacement in existing designs where SDIO and multi-master PCI are unused. However, firmware and hardware initialization must disable SDIO-related registers and configure PCI arbitration for single-master mode to avoid undefined behavior - as the underlying silicon functionality differs despite identical pinout.