STMicroelectronics L6391D

Overview

L6391D from STMicroelectronics is a high-voltage half-bridge gate driver IC for N-channel MOSFETs and IGBTs, featuring 600 V high-side rail capability, ±50 V/ns dV/dt immunity, 290 mA source / 430 mA sink drive strength, 75/35 ns rise/fall times (1 nF load), and integrated bootstrap diode. It enables robust motor control in home appliance inverters and industrial fan drivers.

For engineers reviewing the L6391D datasheet, L6391D pinout, L6391D application, or L6391D equivalent, this page delivers verified technical context, SO-14 package mapping, deadtime-adjustable interlocking logic, smart shutdown propagation delay (200–250 ns), and comparator-based overcurrent protection implementation details.

Technical Context

The L6391D integrates independent high-side (floating) and low-side driver stages with TTL/CMOS-compatible 3.3 V/5 V inputs and hysteresis. Its bootstrap driver uses an internal DMOS switch (R_DS(on) = 120 Ω typ.) instead of an external fast-recovery diode, reducing BOM count and leakage.

It implements hardware-level shoot-through prevention via adjustable deadtime (0.1–3.4 µs via external R_DT) and interlocking logic that forces tri-state output on overlapping HIN/LIN edges. The comparator (pins CP+, CP−) feeds directly into a dedicated fault path with <250 ns turn-off propagation, bypassing SD pin RC delays for immediate shutdown.

Key Specifications

Pinout & Package

Package: SO-14, surface-mount, ECOPACK® compliant, thermal resistance R_th(JA) = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with IR2110PbF and UCC27201D, the L6391D uniquely combines 600 V half-bridge integration, comparator-based fault protection, and adjustable deadtime in a single SO-14 package - reducing total solution size by 35% and eliminating three external components required by alternatives.

Availability

L6391D is available at Aetrix Electronics and suitable for home appliance motor control, industrial fan inverters, HID ballasts, and power supply units requiring stable component supply across multi-year production cycles.

Supply support for L6391D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The L6391D belongs to ST's BCD™ "OFF-LINE" high-voltage driver product line, engineered specifically for robust, compact, and cost-effective AC-DC and motor drive systems operating up to 600 V.

FAQ

What is the maximum allowable bootstrap capacitor discharge voltage drop for reliable L6391D operation?

The L6391D requires V_BOOT − V_OUT ≥ 12.4 V for proper high-side operation. With typical gate charge Q_G = 30 nC and C_BOOT = 100 nF, a 300 mV drop is acceptable. However, internal DMOS R_DS(on) (120 Ω) adds voltage loss during charging - at 5 µs T_CHARGE, drop reaches ~0.7 V. Total drop must stay below 1.6 V to maintain >12.4 V minimum.

How does the L6391D's smart shutdown differ from standard SD pin behavior?

Standard SD pins require external RC networks to set fault disable time, introducing delay between fault detection and output shutdown. The L6391D routes comparator output directly to the gate driver logic, achieving ≤250 ns shutdown propagation - independent of RC values. The SD/OD pin serves only as status indicator and latch interface, not as the primary fault path.

Can the L6391D drive both MOSFETs and IGBTs without modification?

Yes - the L6391D's 290 mA source / 430 mA sink capability and 75/35 ns switching times support gate drive for both 600 V N-channel MOSFETs (e.g., STP16N60M2) and IGBTs (e.g., STGW30NC60WD). No external component changes are needed; only gate resistor selection should be adjusted per device Q_G and desired switching speed.

What layout considerations are critical for maintaining dV/dt immunity in high-noise environments?

To preserve ±50 V/ns dV/dt immunity, minimize parasitic inductance on BOOT, OUT, and HVG traces; place C_BOOT within 5 mm of pins 14 and 12; use separate GND pour for low-side and high-side sections; avoid routing sensitive signals (CP+, CP−, DT) near switching nodes; and ensure >0.3 mm clearance between BOOT and GND traces per 100 V of differential voltage.