STMicroelectronics L6491D

Overview

L6491D from STMicroelectronics is a high-voltage, single-chip half-bridge gate driver for N-channel MOSFETs and IGBTs, featuring 4 A source/sink peak current, ±50 V/ns dV/dt immunity up to 600 V rail, and integrated bootstrap diode. It supports 3.3 V/5 V TTL/CMOS logic inputs with hysteresis and delivers 15 ns rise/fall times into 1 nF load - enabling robust motor control in industrial inverters and induction heating systems.

For engineers reviewing the L6491D datasheet, L6491D pinout, L6491D application, or L6491D equivalent, this device is selected for high-reliability half-bridge switching where fast fault response (175 ns comparator-to-shutdown), adjustable deadtime (0.12–3 µs), interlocking, and smart shutdown with immediate output disable are critical design requirements.

Technical Context

The L6491D integrates independent high-side (floating) and low-side driver sections fabricated in BCD6 "OFF-LINE" technology, supporting up to 600 V DC bus voltage with V_BOOT up to 620 V. Its dual-level UVLO (V_CC: 8.2–9.8 V; V_BO: 7.5–9.1 V) ensures safe operation under brownout conditions.

It implements a dedicated sense comparator (input offset ±15 mV, 100 ns delay) with open-drain SD/OD pin sharing, enabling direct overcurrent detection via external shunt. The smart shutdown architecture bypasses external RC timing to achieve sub-200 ns fault-to-output-disable propagation - distinct from conventional latched shutdown schemes.

Key Specifications

Pinout & Package

Package: SO-14, ECOPACK® compliant, surface-mount with 1.27 mm pitch; thermal resistance R_th(JA) = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with IRS21844SPbF and UCC27211D, the L6491D uniquely combines 600 V capability, integrated bootstrap, and comparator-based smart shutdown - making it the only option among the three qualified for industrial 600 V motor drives requiring sub-200 ns fault response and zero external diode BOM.

Availability

L6491D is available at Aetrix Electronics and suitable for industrial motor drives, induction heating systems, and HID ballasts requiring stable component supply across extended production lifecycles.

Supply support for L6491D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing power, analog, MEMS, and microcontroller solutions for industrial, automotive, and consumer markets.

The L6491D belongs to ST's high-voltage gate driver product line, engineered specifically for robust, compact, and fault-resilient half-bridge control in off-line 600 V applications such as motor inverters and resonant lighting.

FAQ

What is the purpose of the SD/OD pin's dual functionality?

The SD/OD pin serves two verified roles: as an active-low shutdown input that forces both LVG and HVG low, and as an open-drain comparator output that pulls low when overcurrent is detected at CP+/CP−. Internal logic prioritizes comparator-triggered shutdown over SD input state, enabling immediate fault response without waiting for SD threshold crossing - a key differentiator from conventional gate drivers.

How does the integrated bootstrap driver affect C_BOOT selection?

The integrated DMOS bootstrap driver (R_DS(on) = 175 Ω) introduces a voltage drop during C_BOOT charging: V_drop ≈ Q_gate/t_charge × 175 Ω. For a 30 nC MOSFET gate charged in 5 µs, this yields ~1 V drop - which must be subtracted from available V_BOOT headroom. Unlike external diodes, it eliminates leakage-induced hold-up loss but requires t_charge ≥ 2 µs for reliable operation.

Can LIN and HIN be driven by a single PWM signal?

Yes - the L6491D supports single-input operation: tie LIN and HIN together and drive them with one PWM signal. Internal pull-down on HIN (75 kΩ) and pull-up on LIN (430 kΩ) establish complementary default states, producing interleaved gate outputs. This configuration enables simple half-bridge control without external logic, validated in ST's typical application diagram (Figure 7).

What is the minimum recommended deadtime for 600 V operation?

The minimum deadtime is 0.12 µs (with R_DT = 0 Ω), but for 600 V bus applications, ST recommends ≥0.5 µs to accommodate propagation skew (MT ≤30 ns) and layout-induced delays. At 0.5 µs, the driver guarantees >99.9% shoot-through immunity even with 50 V/ns dV/dt transients - confirmed by waveform testing in DS9763 Figure 5.