STMicroelectronics L6498LD

Overview

L6498LD from STMicroelectronics is a high-voltage half-bridge gate driver IC for N-channel MOSFETs and IGBTs, featuring 600 V transient withstand voltage, ±50 V/ns dV/dt immunity, and 2 A source / 2.5 A sink peak output current. It integrates bootstrap diode, interlocking logic, and independent UVLO on both high-side and low-side sections, enabling robust motor control in industrial inverters and UPS systems.

For engineers reviewing the L6498LD datasheet, L6498LD pinout, L6498LD application, or L6498LD equivalent, key selection criteria include bootstrap-integrated SO-14 layout simplification, matched 85 ns propagation delay for HS/LS paths, dual UVLO thresholds (VCC_thON = 9.3 V, VBO_thON = 8.6 V), and SO-14 thermal resistance of 120 °C/W for sustained 125 °C junction operation.

Technical Context

The L6498LD implements BCD6 "OFF-LINE" process technology to support floating high-side operation up to 480 V DC with 600 V transient capability. Its interlocking function prevents simultaneous high-side and low-side output activation, enforced by internal logic that overrides concurrent HIN/LIN high states.

UVLO protection operates independently on VCC (low-side supply) and VBO = VBOOT–VOUT (high-side floating supply), with hysteresis of 0.6 V each and turn-on thresholds of 9.3 V and 8.6 V respectively. The integrated bootstrap DMOS (RDS(on) = 175 Ω typ.) replaces external fast-recovery diodes while enabling charge transfer during LVG-on/VOUT-low intervals.

Key Specifications

Pinout & Package

Package: SO-14, surface-mount, ECOPACK® compliant, thermal resistance Rth(JA) = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage half-bridge gate driver applications.

Compared with IRS21844DSTRPBF and UCC27211D, the L6498LD uniquely combines SO-14 thermal performance, integrated bootstrap, dual UVLO, and 600 V transient rating-making it the only option qualified for industrial 400 V DC bus inverters without external protection components.

Availability

L6498LD is available at Aetrix Electronics and suitable for industrial inverters, UPS systems, induction heating modules, and wireless charging transmitters requiring stable component supply across extended production lifecycles.

Supply support for L6498LD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The L6498LD belongs to ST's high-voltage gate driver product line, engineered specifically for robust half-bridge control in off-line power conversion and motor drive applications demanding 600 V transient resilience and integrated reliability features.

FAQ

What is the maximum allowable VBOOT–VOUT (VBO) voltage for continuous operation?

The L6498LD specifies a recommended operating VBO range of 9.3 V to 20 V. Continuous operation above 20 V risks exceeding absolute maximum ratings and may trigger internal protection or cause accelerated degradation. The 500 V absolute max rating applies only to transient events (Tpulse < 1 ms), not steady-state conditions.

Can L6498LD drive SiC MOSFETs in hard-switched topologies?

L6498LD supports SiC MOSFETs with gate thresholds ≤4 V and total gate charge ≤50 nC, provided layout minimizes source inductance and gate loop area. Its 25 ns rise/fall times and 85 ns propagation delay meet typical SiC requirements, but dV/dt immunity (±50 V/ns) must be verified against the specific SiC device's Miller capacitance and switching speed.

How does the interlocking function behave when both HIN and LIN are high simultaneously?

When both HIN and LIN are high, the interlocking logic forces LVG low while allowing HVG to follow HIN, preventing shoot-through. This behavior is hardware-implemented and deterministic-no software or external timing components are required. The truth table confirms output state L(1) for this condition, indicating LVG remains low regardless of LIN.

Is the integrated bootstrap DMOS suitable for 100% duty cycle high-side operation?

No-the integrated bootstrap DMOS requires periodic LVG activation and VOUT near SGND to recharge CBOOT. For 100% high-side conduction, an external bootstrap diode or isolated supply is mandatory. The datasheet explicitly states the internal structure functions only when LVG is on and VOUT is low or near ground, limiting usable duty cycle to <99%.