STMicroelectronics L6498LDTR

Overview

L6498LDTR from STMicroelectronics is a high-voltage half-bridge gate driver IC for N-channel MOSFETs and IGBTs, featuring 600 V transient withstand voltage, ±50 V/ns dV/dt immunity, and 2 A source / 2.5 A sink peak output current. It integrates bootstrap diode, interlocking logic, and independent UVLO on both high-side and low-side sections, enabling robust motor control in industrial inverters and UPS systems.

For engineers reviewing the L6498LDTR datasheet, L6498LDTR pinout, L6498LDTR application, or L6498LDTR equivalent, key selection criteria include bootstrap-diode integration, SO-14 package thermal resistance (120 °C/W), propagation delay (85 ns typ.), and dual UVLO thresholds (VBO_thON = 8.6 V, VCC_thON = 9.3 V).

Technical Context

The L6498LDTR implements a BCD6 "OFF-LINE" process-based half-bridge driver with floating high-side section rated for 500 V DC rail and 600 V transient voltage. Its interlocking function prevents simultaneous high-side and low-side output activation, while independent UVLO circuits monitor both VCC (8.7 V turn-on) and VBO (8.6 V turn-on) to ensure safe gate drive under undervoltage conditions.

Logic inputs accept 3.3 V or 5 V TTL/CMOS signals with hysteresis (Vih = 2–2.5 V, Vil = 0.95–1.45 V), and internal bootstrap diode (RDS(on) = 175 Ω typ.) eliminates need for external fast-recovery diode-reducing layout complexity and leakage-related boot capacitor discharge.

Key Specifications

Pinout & Package

Package: SO-14, surface-mount, ECOPACK®-compliant, 1.27 mm pitch, 8.55–8.75 mm × 3.80–4.00 mm body size, RthJA = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with IRS21844STRPBF and UCC27211D, the L6498LDTR uniquely combines SO-14 packaging, integrated bootstrap diode, 600 V transient rating, and dual UVLO - making it optimal for compact, high-reliability industrial inverters where layout simplicity and fault resilience are critical.

Availability

L6498LDTR is available at Aetrix Electronics and suitable for industrial motor drives, UPS inverters, induction heating systems, and HID lighting ballasts requiring stable component supply across extended production lifecycles.

Supply support for L6498LDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, microcontrollers, and automotive ICs.

The L6498 belongs to ST's high-voltage gate driver product line, engineered for robust half-bridge control in industrial power conversion-emphasizing integration, fault resilience, and ease of PCB layout.

FAQ

What is the purpose of the separate SGND and PGND pins on the L6498LDTR?

SGND serves as the reference for logic inputs and UVLO comparators to minimize noise coupling from high-current switching paths. PGND provides the return path for LVG output current and VCC supply, isolating power-ground transients from sensitive control circuitry. This separation improves noise immunity and prevents false triggering during high dV/dt events.

Can the L6498LDTR drive 600 V-class IGBTs directly without external level-shifting components?

Yes-the L6498LDTR's high-side section is rated for 600 V transient withstand voltage and operates with a floating OUT pin referenced to the switch node. When configured with proper bootstrap capacitance and layout, it directly drives the gate of 600 V IGBTs in half-bridge topologies without external level shifters or isolated supplies.

How does the interlocking function prevent shoot-through in the L6498LDTR?

The interlocking logic hardware-enforces that HIN and LIN cannot both be high simultaneously. If both inputs go high, the internal circuitry forces LVG low before HVG can activate, introducing a controlled dead-time. This eliminates shoot-through risk without requiring external timing circuitry or MCU-level dead-time insertion.

What is the minimum recommended CBOOT value for a 30 nC gate charge MOSFET at 100 kHz switching?

For a 30 nC gate charge MOSFET at 100 kHz (10 µs period), assuming 50% duty cycle and 5 µs charging window, a 100 nF CBOOT yields ~300 mV voltage drop due to gate charge alone. Accounting for 120 µA HVG quiescent current over 5 ms TON adds ~0.6 V drop-so ≥220 nF is recommended to keep total VBO droop under 1 V for reliable high-side operation.