STMicroelectronics L6747C

Overview

L6747C from STMicroelectronics is a dual high-current N-channel MOSFET driver for synchronous buck converters, featuring adaptive dead-time control, 5–12 V flexible gate-drive voltage, preliminary overvoltage (OV) protection triggered at ~1.8 V on PHASE, and HiZ management via EN/PWM inputs. It drives both high-side and low-side MOSFETs in CPU VRM/VRD and high-efficiency DC-DC applications up to high switching frequencies.

For engineers reviewing the L6747C datasheet, L6747C pinout, L6747C application, or L6747C equivalent, key selection criteria include its 3.5 A peak source/sink capability per channel, VFDFPN8 3×3 mm thermal performance (R_THJC = 5 °C/W), anti-shoot-through logic, and boot-capacitor–dependent high-side drive architecture - all critical for stable high-current VRM design.

Technical Context

The L6747C implements independent high-side (BOOT/PHASE-referenced) and low-side (VCC/GND-referenced) drivers with integrated anti-shoot-through logic and adaptive dead-time adjustment based on PHASE voltage transitions. Its propagation delays are tightly specified (t_{prop_H} = 30–45 ns, t_{prop_L} = 25–35 ns) to support high-frequency operation above 1 MHz.

HiZ state is entered either by pulling EN low or by holding PWM within 1.3–1.6 V for >120 ns; during HiZ, preliminary OV protection monitors PHASE and latches LGATE ON if voltage exceeds ~1.8 V - a hardware-level safeguard active before controller initialization. UVLO thresholds (V_CC turn-on = 4.1 V, turn-off = 3.5 V) ensure safe power-up sequencing.

Key Specifications

Pinout & Package

Package: VFDFPN8 (Very thin Fine-pitch Dual Flat Package No-lead), 3 mm × 3 mm, 0.5 mm pitch, exposed thermal pad (TH.PAD) for enhanced thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual high-current MOSFET driver applications.

Compared with IR2110PbF and LM5113MMX/NOPB, the L6747C uniquely integrates adaptive dead-time, preliminary OV latching, and dual-path HiZ entry - making it purpose-built for high-reliability, high-current CPU VRM systems where startup safety and timing precision are non-negotiable.

Availability

L6747C is available at Aetrix Electronics and suitable for desktop CPU VRM, server VRD power stages, and high-efficiency point-of-load DC-DC converters requiring stable component supply, long-term lifecycle continuity, and traceable sourcing.

Supply support for L6747C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, microcontrollers, and automotive ICs with strong European manufacturing and R&D infrastructure.

The L6747C belongs to ST's high-performance power driver product line, engineered specifically for synchronous buck topologies in computing power delivery - emphasizing reliability, thermal efficiency, and hardware-level fault protection for mission-critical CPU/GPU supplies.

FAQ

What is the function of the PHASE pin beyond being the high-side return path?

The PHASE pin serves three critical roles: (1) return path for the high-side driver, (2) input for adaptive dead-time control by sensing voltage slew rate during HS turn-off, and (3) sensing node for preliminary OV protection - triggering LGATE latch-on if voltage exceeds 1.7–1.8 V during HiZ. It is not a passive node; internal clamp circuitry prevents leakage during disable states.

Can the L6747C operate with a 5 V-only supply, and what impact does that have on performance?

Yes, the L6747C operates with VCC = 5 V (minimum UVLO turn-on is 4.1 V). At 5 V, LS drive strength remains full (3.5 A), but HS gate voltage (BOOT–PHASE) is limited to ~5 V, increasing R_DS(on) losses in high-current HS MOSFETs. For optimal efficiency in >100 A VRMs, 12 V VCC is recommended to maximize HS gate overdrive and reduce conduction loss.

How does the HiZ window (1.3–1.6 V on PWM) interact with standard 3.3 V or 5 V logic signals?

The HiZ window is intentionally narrow and centered below standard logic-high thresholds (VPWM_IH = 2 V min). It is not intended for general logic signaling but for dedicated HiZ coordination - e.g., a controller can pull PWM to 1.45 V using a resistor divider during soft shutdown. External noise filtering is required, as the 300 mV window demands clean, slew-controlled transitions to avoid spurious HiZ entry.

Is an external bootstrap diode required, and why does the datasheet omit it?

No external bootstrap diode is required: the L6747C integrates a charge-transfer diode between VCC and BOOT. This internal diode enables automatic bootstrap capacitor charging during LS conduction. The omission reflects integration - unlike legacy drivers (e.g., IR2110), the L6747C eliminates this discrete component, reducing BOM count and layout complexity while maintaining reliable high-side drive.