STMicroelectronics L6747CTR

Overview

L6747CTR from STMicroelectronics is a dual high-current N-channel MOSFET driver for synchronous buck converters, featuring adaptive dead-time control, 5–12 V flexible gate-drive supply, preliminary overvoltage (OV) protection triggered at 1.8 V on PHASE, and HiZ shutdown via EN or PWM window detection. It drives high-side and low-side MOSFETs in CPU VRM/VRD and high-efficiency DC-DC applications up to multi-MHz switching frequencies.

For engineers reviewing the L6747CTR datasheet, L6747CTR pinout, L6747CTR application, or L6747CTR equivalent, key selection criteria include boot-capacitor design guidance, PHASE-pin-based OV threshold accuracy, propagation delay matching (25–45 ns), thermal resistance (R_THJC = 5 °C/W), and VFDFPN8 3×3 mm package layout constraints for high-current power stages.

Technical Context

The L6747CTR implements independent high-side (BOOT/PHASE-referenced) and low-side (VCC/GND-referenced) drivers with anti-shoot-through logic and adaptive dead-time adjustment based on PHASE voltage slew rate. Its HiZ management responds to either EN pin deassertion or PWM input held between 1.3 V–1.6 V for >120 ns.

Preliminary OV protection activates only after VCC exceeds UVLO (4.1 V) and while in HiZ state, latching LGATE ON if PHASE rises above 1.8 V - a hardware-level safeguard against high-side MOSFET failure during startup, independent of external PWM controller behavior.

Key Specifications

Pinout & Package

VFDFPN8 3×3 mm package with exposed thermal pad (TH.PAD) for direct connection to PGND plane; 0.5 mm pitch, 8-terminal leadless construction compliant with ECOPACK® environmental standards.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET driver applications.

Compared with IR2110PbF and LM5113MMX/NOPB, the L6747CTR delivers tightly coupled timing, hardware-based safety features (pre-OV, HiZ), and VRM-optimized drive strength - making it uniquely suited for high-current, low-voltage synchronous buck applications where reliability and efficiency are co-constrained.

Availability

L6747CTR is available at Aetrix Electronics and suitable for desktop CPU VRM, server VRD, and workstation GPU power delivery systems requiring stable component supply, long-term lifecycle support, and consistent thermal performance in compact 3×3 mm packages.

Supply support for L6747CTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, analog, and microcontroller solutions for automotive, industrial, and computing markets.

The L6747CTR belongs to ST's high-performance power driver product line, engineered specifically for synchronous buck topologies in high-current CPU/GPU voltage regulator modules where timing precision, thermal efficiency, and hardware-level fault protection are critical.

FAQ

What is the function of the PHASE pin beyond being the high-side driver return path?

The PHASE pin serves three critical roles: (1) return path for the high-side driver, (2) input for adaptive dead-time control by sensing voltage slew rate during HS turn-off, and (3) sensing node for preliminary OV protection - triggering LGATE latch-on if voltage exceeds 1.8 V during HiZ. It directly connects to the high-side MOSFET source and must be routed with minimal inductance.

How does the L6747CTR implement "adaptive" dead-time, and how is it different from fixed dead-time drivers?

Adaptive dead-time is determined dynamically by monitoring the falling edge of the PHASE node voltage. When the HS MOSFET turns off, the driver waits until PHASE falls below a threshold before enabling the LS MOSFET - eliminating fixed delays and minimizing LS body-diode conduction time across varying load and temperature conditions. This contrasts with fixed dead-time drivers that use static timing, risking shoot-through or excessive conduction loss.

Can the L6747CTR operate with a 5 V-only supply, and what impact does this have on gate-drive strength?

Yes - the L6747CTR supports VCC and BOOT supplies independently from 5 V to 12 V. At 5 V, UGATE and LGATE peak source/sink currents reduce proportionally (e.g., ~1.5 A vs. 3.5 A at 12 V), but remain sufficient for low-R_DS(on) MOSFETs used in 5 V-input VRMs. Drive strength scales with supply voltage, so 5 V operation trades some switching speed for lower gate-drive loss and improved compatibility with 5 V logic interfaces.

What layout practices are mandatory to ensure reliable operation of the VFDFPN8 package at high current?

Mandatory practices include: (1) connecting the exposed thermal pad (TH.PAD) to a dedicated PGND plane using ≥6 thermal vias, (2) placing 1 μF low-ESR MLCCs within 2 mm of VCC and BOOT pins, (3) routing UGATE/LGATE traces as short/wide as possible (<5 mm, ≥0.3 mm width), and (4) avoiding splits in the PHASE/GND return paths to prevent noise coupling into adaptive timing circuits.