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Texas Instruments LM10504TME/NOPB
- Part No.:
- LM10504TME/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 34-WFBGA
- Datasheet:
-
LM10504TME/NOPB.pdf
- Description:
- IC SSD TRPL BUCK + LDO 34USMD
- Quantity:
- Payment:
- Shipping:
Inventory:550
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Product details
Overview
LM10504TME/NOPB from Texas Instruments is a triple-buck + LDO power management IC designed for SSD and flash controller SoC power delivery. It integrates three synchronous buck regulators (Buck 1: 1.1–3.6 V / 1.6 A; Buck 2: 1.1–3.6 V / 1 A; Buck 3: 0.7–1.335 V / 1 A) and one programmable 1.2–3.1 V / 250 mA LDO, all controlled via SPI interface with 2-MHz switching frequency and ±3% feedback accuracy.
For engineers reviewing the LM10504TME/NOPB datasheet, LM10504TME/NOPB pinout, LM10504TME/NOPB application, or LM10504TME/NOPB equivalent, key selection criteria include SPI-programmable voltage sequencing, DevSLP-enabled deep-sleep mode, integrated comparator interrupt output, and DSBGA-34 package compatibility with high-density SSD layouts.
Technical Context
The LM10504TME/NOPB implements phase-shifted interleaving across its three buck regulators to reduce input ripple and minimize required input capacitance. Each buck uses integrated high-side/low-side FETs (RDS(on)-HS = 135 mΩ typ, RDS(on)-LS = 85 mΩ typ) and supports PFM mode at light loads for >90% peak efficiency.
Its SPI-controlled architecture enables dynamic voltage scaling in coordination with host controllers, while the dedicated DevSLP pin triggers coordinated shutdown of core, flash, and I/O rails. The analog comparator monitors VCOMP (2–4 V range) and asserts an open-drain Interrupt signal with 6 µs typical transition time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck 1 Output | 1.1–3.6 V / 1.6 A; supports bypass mode for ultra-low IQ operation |
| Buck 3 Output | 0.7–1.335 V / 1 A; optimized for low-voltage SoC core domains |
| LDO Output | 1.2–3.1 V / 250 mA; 160 mV dropout at full load ensures stable I/O rail under transient |
| Switching Frequency | 2 MHz (±25% over temp); enables use of compact 2.2 µH inductors and 4.7 µF ceramic input caps |
| Feedback Accuracy | ±3%; guarantees tight regulation for sensitive memory controller VDDQ and VCCQ rails |
| SPI Interface | Up to 10 MHz; enables real-time voltage updates and register readback without external MCU intervention |
| Thermal Protection | Thermal shutdown at 140°C; automatic recovery at 120°C prevents latch-up during sustained overload |
Pinout & Package
LM10504TME/NOPB is housed in a 2.80 mm × 2.80 mm, 34-ball DSBGA (YFR) package with 0.5-mm pitch and bottom-side thermal pad. Ball assignment follows TI's standard DSBGA layout for optimal PCB thermal dissipation and minimal trace inductance on high-current paths.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN_B1, VIN_B2, VIN_B3 | Buck input power supply pins | Accept 3–5.5 V input; each must be decoupled locally with ≥4.7 µF ceramic cap to sustain peak current demands |
| SW_B1, SW_B2, SW_B3 | Power switch node outputs | Connect directly to respective buck inductors; require short, low-inductance routing to minimize EMI and switching loss |
| FB_B1, FB_B2, FB_B3 | Output voltage feedback inputs | Resistive divider connection point; bias current <5 µA enables high-impedance dividers for precision setting |
| SPI_CS, SPI_CLK, SPI_DI, SPI_DO | SPI serial interface signals | Support 10-MHz operation; DI/DO are CMOS-level compatible with 1.72–3.63 V IO supply (VIN_IO) |
| DevSLP | Deep-sleep enable input | Active-high with internal pulldown; initiates coordinated shutdown sequence reducing system quiescent current to 100 µA |
| Interrupt | Comparator output | Open-drain output asserting when VCOMP crosses 2.74–2.79 V window; requires external pullup for host interrupt detection |
Key Features
| Feature | Design Value |
|---|---|
| Phase-shifted buck operation | Reduces input ripple amplitude by >50% vs. non-interleaved design, cutting required bulk capacitance by ~3× |
| Programmable start-up sequencing | Enables custom voltage ramp order (e.g., LDO before Bucks) to meet ASIC power-on reset timing requirements |
| Power-down data protection | Automatically holds critical rail voltages during host-initiated suspend, preventing data corruption in NAND flash buffers |
| Bypass mode on Bucks 1 & 2 | Disables switching and engages integrated FETs as low-RDS(on) pass elements, reducing IQ to 15 µA per channel |
| VSELECT logic pins | Hardware-selectable startup voltages for Buck 2/Buck 3 eliminate need for SPI initialization in boot-critical paths |
Applications
| Solid-State Drive (SSD) Controller Power | Embedded Flash Memory System |
|---|---|
Use Scenario: Powering multi-rail ASIC in PCIe/NVMe SSD with independent core, cache, and I/O domains. IC Role / Device Role / Timing Role: Primary PMU delivering sequenced, SPI-dynamic Vcore (0.7–1.335 V), Vccq (1.2–3.1 V), and Vhost (3.0 V) rails. Use Value: Phase-shifted bucks cut input capacitor count by 2×; DevSLP support reduces idle power by >90% during host sleep states. |
Use Scenario: Supplying eMMC/UFS host controller with strict voltage accuracy and fast transient response. IC Role / Device Role / Timing Role: Single-chip solution generating VCC (3.0 V/1.6 A), VCCQ (3.0 V/1 A), and Vcore (1.2 V/1 A) with synchronized startup. Use Value: ±3% feedback accuracy maintains NAND interface timing margins; 2-MHz switching enables <1 mm² inductor footprint per rail. |
| Low-Power IoT Storage Module | Industrial Embedded Flash Controller |
Use Scenario: Battery-powered edge device requiring ultra-low quiescent current during extended standby. IC Role / Device Role / Timing Role: Enables deep-sleep mode via DevSLP pin, shutting down non-essential bucks while maintaining LDO bias for wake-up circuitry. Use Value: Achieves 100 µA total system IQ in DevSLP state-critical for >1-year battery life in remote logging applications. |
Use Scenario: Ruggedized industrial SSD operating across –30°C to +85°C ambient with high reliability demand. IC Role / Device Role / Timing Role: Provides thermally robust power with junction-to-board RθJB = 39°C/W and overtemperature lockout at 140°C. Use Value: Integrated thermal shutdown and UVLO/OVLO protect against field failures due to power supply anomalies or heatsink degradation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65295RGER | Triple buck + dual LDO; no integrated comparator; 3-MHz switching; supports I²C only | Lacks DevSLP and SPI-programmable comparator; better suited for general-purpose SoC vs. SSD-specific sequencing | Choose when I²C interface suffices and comparator functionality is handled externally |
| RTQ2134BGQW | Dual buck + single LDO; no SPI interface; fixed-output variants only; 2-MHz switching | No voltage programmability or sequencing control; requires external GPIOs for rail enable sequencing | Choose for cost-sensitive designs where fixed voltages and simpler control are acceptable |
Compared with TPS65295RGER and RTQ2134BGQW, LM10504TME/NOPB uniquely combines SPI-based dynamic voltage scaling, hardware DevSLP coordination, and integrated interrupt comparator-making it the only option qualified for high-performance SSD controller power with data-integrity safeguards.
Availability
LM10504TME/NOPB is available at Aetrix Electronics and suitable for solid-state drive development, embedded flash controller design, and industrial storage module production requiring stable component supply and long-term lifecycle assurance.
Supply support for LM10504TME/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design for high-reliability applications.
The LM10504TME/NOPB belongs to TI's SSD-optimized PMU product line, engineered specifically to meet the dynamic voltage, sequencing, and low-power sleep requirements of NAND flash controller SoCs.
FAQ
What is the maximum supported SPI clock frequency for LM10504TME/NOPB?
The LM10504TME/NOPB supports SPI communication up to 10 MHz across its full operating temperature range (–30°C to +85°C). This allows rapid register writes for dynamic voltage scaling during SSD active/idle transitions. All SPI transactions on LM10504TME/NOPB are edge-triggered on the rising clock, with CS active-low assertion required for valid command framing.
Does LM10504TME/NOPB support independent enable/disable of each buck regulator?
Yes, LM10504TME/NOPB provides individual software-controlled enable bits for Buck 1, Buck 2, and Buck 3 via its SPI register map. Each buck can be disabled independently while others remain active-enabling flexible power domain control during partial system sleep. Hardware disable is not supported; all enables are register-mapped and require SPI access.
What is the purpose of the VSELECT_B2 and VSELECT_B3 pins on LM10504TME/NOPB?
VSELECT_B2 and VSELECT_B3 are hardware configuration pins that set default startup voltages for Buck 2 and Buck 3 prior to SPI initialization. VSELECT_B2 is internally pulled down (defaulting Buck 2 to 1.8 V), and VSELECT_B3 is internally pulled up (defaulting Buck 3 to 1.2 V). These pins ensure safe boot voltage levels even if SPI firmware fails to configure rails early in power-up.
How does LM10504TME/NOPB handle thermal overload conditions?
LM10504TME/NOPB incorporates internal thermal shutdown that activates at TJ = 140°C and releases at TJ = 120°C (typical hysteresis). When triggered, all bucks and the LDO shut down simultaneously while preserving register contents. The device resumes normal operation automatically upon cooling-no external reset or SPI reinitialization is required for LM10504TME/NOPB recovery.
Can LM10504TME/NOPB operate with different input voltages on VIN_B1, VIN_B2, and VIN_B3?
Yes, LM10504TME/NOPB allows independent input supplies: VIN_B1, VIN_B2, and VIN_B3 may be driven from separate sources (e.g., 5 V for Buck 1, 3.3 V for Buck 2/3). Each input must meet its respective recommended operating range (3–5.5 V), and unused inputs must be tied to GND to minimize leakage. This flexibility supports mixed-input architectures common in modular SSD power systems.
LM10504TME/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 34-WFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- Solid State Drives (SSD)
- Current - Supply:
- 15µA
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -30°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 34-µSMD (2.82x2.82)
LM10504TME/NOPB FAQ
1.How can I place an order for LM10504TME/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM10504TME/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM10504TME/NOPB reliable?
The price and inventory of LM10504TME/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM10504TME/NOPB is usually 5 days.
3.What payment methods are accepted for LM10504TME/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM10504TME/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM10504TME/NOPB?
LM10504TME/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM10504TME/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM10504TME/NOPB?
For technical support, including LM10504TME/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM10504TME/NOPB requirements.
6.How does Aetrix verify that LM10504TME/NOPB is sourced from the original manufacturer or authorized distributors?
All LM10504TME/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM10504TME/NOPB meets industry standards.
7.What is the process for return or replacement of LM10504TME/NOPB?
All LM10504TME/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM10504TME/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM10504TME/NOPB part is unused and in its original packaging.
Return procedure for LM10504TME/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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