Texas Instruments LM10506TME-A/NOPB

Overview

LM10506TME-A/NOPB from Texas Instruments is a triple-buck + LDO power management IC for SoC/ASIC systems, delivering 1.3 A at 1.1–3.6 V (Buck 1), 400 mA at 2.0 V (Buck 2, fixed per TME-A variant), and 600 mA at 0.7–1.335 V (Buck 3), plus a 3.2 V/100 mA LDO - all in a 2.84 mm × 2.84 mm DSBGA-34 package.

For engineers reviewing the LM10506TME-A/NOPB datasheet, LM10506TME-A/NOPB pinout, LM10506TME-A/NOPB application, or LM10506TME-A/NOPB equivalent, this PMU supports SPI-programmable voltage sequencing, phase-shifted 2 MHz buck operation, PFM/PWM mode selection, interrupt comparator, and standby/reset control - critical for SSD, embedded storage, and low-power host controller power domains.

Technical Context

The LM10506TME-A/NOPB integrates three synchronous buck regulators with voltage-mode control, 120° phase interleaving to reduce input ripple, and internal compensation optimized for 2.2 µH inductors and 4.7–100 µF ceramic output capacitors. Each buck features integrated high-side (135–260 mΩ) and low-side (85–190 mΩ) FETs, ±3% feedback accuracy, and programmable soft-start.

It includes an SPI interface (up to 10 MHz) for real-time output voltage adjustment, sequencing control, and status register readback; a dedicated 2–4 V programmable comparator with IRQ output; and digital control pins (STANDBY, RESET, HL_B2/HL_B3) enabling hardware-triggered voltage configuration and power-state transitions without SPI intervention.

Key Specifications

Pinout & Package

LM10506TME-A/NOPB uses a 34-ball DSBGA package (2.84 mm × 2.84 mm, 0.4 mm pitch) with exposed thermal pad. Ball assignment follows TI's standard top-view layout with dedicated VIN, SW, FB, GND, and SPI signal groups.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMU applications.

Compared with TPS65023RSBR and MAX20029ATP/V+T, LM10506TME-A/NOPB uniquely combines SPI-programmable triple bucks with hardware-selectable outputs, phase interleaving, and integrated comparator - making it optimal for SSDs requiring dynamic voltage scaling and compact DSBGA packaging.

Availability

LM10506TME-A/NOPB is available at Aetrix Electronics and suitable for solid-state drives, embedded storage controllers, and industrial flash modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LM10506TME-A/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in high-efficiency DC/DC conversion and system-level power architecture.

The LM10506 product line was engineered specifically for high-density storage applications - integrating triple buck regulation, LDO, and SPI-controlled sequencing into a single DSBGA die to replace discrete PMU solutions in SSDs and embedded controllers.

FAQ

What is the fixed output voltage of Buck 2 in LM10506TME-A/NOPB?

The LM10506TME-A/NOPB variant has Buck 2 factory-configured to 2.0 V, as confirmed in TI's Device Comparison Table (SNVS729F, Table 1). This differs from the base LM10506TME (3.0 V Buck 2) and is selected via the HL_B2 pin's default state. The 2.0 V output aligns with JEDEC VCCQ requirements for LPDDR interfaces in SSD controllers.

Does LM10506TME-A/NOPB support hardware-based voltage selection without SPI communication?

Yes. LM10506TME-A/NOPB uses the HL_B2 and HL_B3 pins to select Buck 2 and Buck 3 startup voltages in hardware. HL_B2 is internally pulled down, fixing Buck 2 to 2.0 V; HL_B3 is internally pulled up, setting Buck 3 to 1.335 V. These pins enable boot-time configuration before SPI initialization, critical for early-system power-up sequencing.

What is the maximum supported SPI clock frequency for LM10506TME-A/NOPB?

The LM10506TME-A/NOPB supports SPI clock frequencies up to 10 MHz, as specified in Section 7.5 (Digital Interface) of the datasheet. This allows rapid register writes for dynamic voltage scaling - for example, adjusting Buck 1 output from 1.1 V to 3.6 V in under 100 µs - essential for performance-state transitions in SSD firmware.

How does the phase-shifted buck operation benefit LM10506TME-A/NOPB in SSD applications?

LM10506TME-A/NOPB operates its three bucks at 120° phase offset, reducing input capacitor RMS current by ~40% compared to in-phase operation. This allows use of smaller 4.7 µF input ceramics instead of larger tantalum or polymer caps - saving PCB area and improving reliability in thermally constrained SSD modules where space and thermal management are critical.

What protection features are integrated into LM10506TME-A/NOPB?

LM10506TME-A/NOPB includes undervoltage/overvoltage lockout (UVLO/OVLO), thermal shutdown (140°C trip, 120°C release), peak current limiting (1.6–1.7 A per buck), automatic soft-start, and short-circuit protection on the LDO. These features ensure robust operation during input transients, overloads, or elevated ambient temperatures common in industrial SSD deployments.