Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Texas Instruments LM26484SQ/NOPB

Name: LM26484SQ/NOPB
Brand: Texas Instruments
SKU: LM26484SQ/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LM26484SQ/NOPB

Manufacturer:: Texas Instruments

Category:: Power Management - Specialized

Package:: 24-WFQFN Exposed Pad

Datasheet:: LM26484SQ/NOPB.pdf

Description:: IC PMU REG BUCK/LDO DUAL 24WQFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,196

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LM26484SQ/NOPB from Texas Instruments is a dual-buck + LDO controller power management unit for FPGA/ASIC core and I/O rail sequencing in automotive infotainment and networking routers. It integrates two 2.0A synchronous buck converters (0.8–3.5V output, ±1% V_FB accuracy), one NMOS LDO controller (0.8–1.5V, ±1.5% V_FB), 2 MHz PWM switching, and active low nPOR with 60–475 ms delay.

For engineers reviewing the LM26484SQ/NOPB datasheet, LM26484SQ/NOPB pinout, LM26484SQ/NOPB application, or LM26484SQ/NOPB equivalent, this device supports flexible multi-rail sequencing with independent enable control (ENSW1/ENSW2/ENLDO), 180° phase-shifted buck clocks to reduce input ripple, and low-dropout 100% duty-cycle operation for post-regulation of Buck2-supplied rails.

Technical Context

The LM26484SQ/NOPB uses voltage-mode PWM control with input-voltage feed-forward for tight line regulation and synchronous rectification via internal NFETs to maximize efficiency at low V_OUT. Its dual-buck architecture operates with 180° phase shift to minimize input capacitor RMS current and peak demand.

The integrated LDO controller drives an external NMOS FET in LI-LO configuration, supporting regulated-to-low-VIN operation when powered from Buck2. Thermal shutdown engages at 160°C (typ.) and disengages at 130°C (typ.), with overcurrent protection limiting peak switch current to 3.2 A.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	3.0–5.5 V - Supports single-supply operation from common 3.3 V or 5 V system rails.
Buck Output Current	2.0 A per channel - Sustains full load across −40°C to +125°C junction temperature range.
Feedback Accuracy	±1.0% for bucks, ±1.5% for LDO - Ensures precise core voltage regulation critical for FPGA/ASIC timing margins.
Switching Frequency	2.0 MHz (typ.) - Enables use of small 0.5 µH inductors and compact 10–22 µF ceramic output capacitors.
nPOR Delay	60–475 ms - Provides configurable reset assertion time for sequenced power-up of downstream logic.
Thermal Shutdown	160°C (typ.) - Protects against sustained overload or poor PCB thermal design without latch-up.
LDO Output Range	0.8–1.5 V - Matches analog supply requirements for ADCs, PLLs, and SerDes PHYs.

Pinout & Package

LM26484SQ/NOPB is housed in a 5 mm × 4 mm × 0.8 mm WQFN-24 package (TI package code NHZ0024B) with exposed thermal pad (DAP) connected to GND for enhanced heat dissipation.

Pin/Terminal	Circuit Role	Design Meaning
VIN1, VIN2	Power Input	Dual independent DC inputs for Buck1 and Buck2; each accepts 3.0–5.5 V.
SW1, SW2	Switch Node	High-side PMOS + low-side NMOS switch outputs; require external inductor and output capacitor.
FB1, FB2, LDOFB	Feedback Input	Resistor-divider nodes setting output voltage; internal 0.5 V reference enables precise V_OUT programming.
ENSW1, ENSW2, ENLDO	Enable Control	Active-high digital inputs enabling/disabling each regulator independently for custom power sequencing.
nPOR	Reset Output	Open-drain active-low reset signal asserting until all supplies stabilize and internal timer expires.
PGND_SW1, PGND_SW2, AGND, GND	Ground Return	Separate power and analog grounds minimize noise coupling between switching and sensitive analog circuits.

Key Features

Feature	Design Value
180° Phase-Shifted Buck Clocks	Reduces input capacitor RMS current by ~30%, allowing smaller bulk capacitance and lower EMI.
Auto PFM/PWM Mode Switching	Maintains >85% efficiency at light loads (I_OUT < 70 mA) while delivering high precision under full load.
100% Duty-Cycle Low-Dropout Operation	Supports V_OUT regulation even when V_IN drops within ~100 mV of target, critical for battery-backed systems.
Integrated Soft Start	Ramps output voltage linearly over ~500 µs to limit inrush current and prevent system brownouts during startup.
Thermal & Overcurrent Protection	Combines junction temperature monitoring and cycle-by-cycle peak current limiting (3.2 A) for robust fault handling.

Applications

Automotive Infotainment Systems	Networking Routers
Use Scenario: Powering multi-core SoC, DDR memory, and display interface in head-unit ECUs with strict thermal and EMI constraints. IC Role / Device Role / Timing Role: Dual-buck supplies core (1.0–1.2 V) and I/O (1.8–3.3 V) rails; LDO powers low-noise analog audio codec. Use Value: Phase-shifted switching reduces input ripple amplitude by 40%, easing compliance with CISPR-25 Class 5 emissions limits.	Use Scenario: Sequencing power for Ethernet PHYs, packet processors, and USB controllers in compact residential gateways. IC Role / Device Role / Timing Role: Buck1 powers 1.2 V CPU core; Buck2 supplies 3.3 V I/O; LDO delivers clean 1.5 V to SerDes reference clock generator. Use Value: Independent enable pins allow staggered startup to avoid inrush current exceeding 5 A peak on shared 5 V input rail.
FPGA-Based Industrial Controllers	Set-Top Box Platforms
Use Scenario: Managing dynamic voltage scaling for Xilinx Artix-7 FPGA banks requiring separate 1.0 V, 1.8 V, and 3.3 V supplies. IC Role / Device Role / Timing Role: Buck1 (1.0 V) for FPGA core; Buck2 (1.8 V) for transceivers; LDO (1.2 V) for PLL analog supply. Use Value: ±1% feedback accuracy ensures setup/hold timing margins remain intact across temperature and load variation.	Use Scenario: Supplying triple-rail power to Broadcom BCM7xxx SoC, HDMI transmitter, and tuner IC in cost-sensitive consumer devices. IC Role / Device Role / Timing Role: Buck1 (1.2 V) for SoC core; Buck2 (3.3 V) for peripherals; LDO (1.0 V) for RF front-end bias. Use Value: 2 MHz switching frequency allows use of 0603-size inductors and 0402 MLCCs, reducing total BOM area by 35% vs. 500 kHz solutions.

Automotive Infotainment Systems

Networking Routers

Use Scenario: Powering multi-core SoC, DDR memory, and display interface in head-unit ECUs with strict thermal and EMI constraints.

IC Role / Device Role / Timing Role: Dual-buck supplies core (1.0–1.2 V) and I/O (1.8–3.3 V) rails; LDO powers low-noise analog audio codec.

Use Value: Phase-shifted switching reduces input ripple amplitude by 40%, easing compliance with CISPR-25 Class 5 emissions limits.

Use Scenario: Sequencing power for Ethernet PHYs, packet processors, and USB controllers in compact residential gateways.

IC Role / Device Role / Timing Role: Buck1 powers 1.2 V CPU core; Buck2 supplies 3.3 V I/O; LDO delivers clean 1.5 V to SerDes reference clock generator.

Use Value: Independent enable pins allow staggered startup to avoid inrush current exceeding 5 A peak on shared 5 V input rail.

FPGA-Based Industrial Controllers

Set-Top Box Platforms

Use Scenario: Managing dynamic voltage scaling for Xilinx Artix-7 FPGA banks requiring separate 1.0 V, 1.8 V, and 3.3 V supplies.

IC Role / Device Role / Timing Role: Buck1 (1.0 V) for FPGA core; Buck2 (1.8 V) for transceivers; LDO (1.2 V) for PLL analog supply.

Use Value: ±1% feedback accuracy ensures setup/hold timing margins remain intact across temperature and load variation.

Use Scenario: Supplying triple-rail power to Broadcom BCM7xxx SoC, HDMI transmitter, and tuner IC in cost-sensitive consumer devices.

IC Role / Device Role / Timing Role: Buck1 (1.2 V) for SoC core; Buck2 (3.3 V) for peripherals; LDO (1.0 V) for RF front-end bias.

Use Value: 2 MHz switching frequency allows use of 0603-size inductors and 0402 MLCCs, reducing total BOM area by 35% vs. 500 kHz solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck + LDO controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65270RGET	Single 3-A buck + dual 1.5-A bucks; no integrated LDO controller; requires external FET for linear regulation.	Higher total current capacity but lacks dedicated NMOS LDO driver for ultra-low-noise analog rails.	Select when higher current per buck is required and discrete LDO implementation is acceptable.
LM2743MMX/NOPB	Single 3-A buck + LDO controller; no second buck; supports only one adjustable output besides LDO.	Simpler sequencing for dual-rail systems where only one switched rail is needed alongside LDO.	Select for space-constrained designs needing only one high-current buck plus analog LDO support.

Compared with TPS65270RGET and LM2743MMX/NOPB, the LM26484SQ/NOPB uniquely combines dual 2-A bucks with a dedicated NMOS LDO controller in one WQFN-24 package-enabling three independent, precisely sequenced rails without external pass FETs or additional controllers.

Availability

LM26484SQ/NOPB is available at Aetrix Electronics and suitable for automotive infotainment, networking routers, FPGA-based industrial controllers, and set-top box platforms requiring stable component supply across extended temperature and long production lifecycles.

Supply support for LM26484SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 90 years of innovation history.

The LM26484SQ/NOPB belongs to TI's Power Management Unit (PMU) product line, designed specifically for multi-rail, thermally constrained applications in automotive, industrial, and communications equipment where sequencing, efficiency, and reliability are critical.

FAQ

What is the maximum output current capability of each buck converter in the LM26484SQ/NOPB?

The LM26484SQ/NOPB supports up to 2.0 A continuous output current per buck channel (Buck1 and Buck2) across the full operating temperature range of −40°C to +125°C. This rating assumes proper PCB layout with adequate copper area for thermal dissipation and use of recommended external components including a 0.5 µH inductor and 22 µF ceramic output capacitor. Peak switch current is limited to 3.2 A for overload protection.

Does the LM26484SQ/NOPB support automatic power sequencing between its regulators?

No, the LM26484SQ/NOPB does not include built-in autonomous sequencing logic. Instead, it provides independent enable inputs (ENSW1, ENSW2, ENLDO) that must be driven by an external microcontroller, CPLD, or power sequencer to implement custom startup/shutdown order. This architecture gives designers full control over timing intervals and fault response, unlike fixed-sequence PMUs.

Can the LM26484SQ/NOPB operate with input voltage below 3.0 V?

No-the absolute minimum operating input voltage for the LM26484SQ/NOPB is 3.0 V across VIN1, VIN2, AVDD, and AVIN pins. Operation below this threshold will cause undervoltage lockout (UVLO) activation, disabling all regulators and holding nPOR low. The device is not rated for sub-3.0 V operation, and attempting to run below this level may result in unstable regulation or undefined behavior.

What is the purpose of the nPOR pin on the LM26484SQ/NOPB, and how is its delay determined?

The nPOR pin on the LM26484SQ/NOPB is an active-low open-drain power-on reset output that remains asserted (low) until all internal supplies stabilize and a programmable delay elapses. Its delay ranges from 60 ms to 475 ms depending on process, voltage, and temperature; it is not user-adjustable. The delay ensures downstream logic receives a clean, synchronized reset after all rails reach regulation, preventing metastability in FPGAs or microcontrollers.

How does the LM26484SQ/NOPB achieve low-noise performance for analog LDO applications?

The LM26484SQ/NOPB achieves low-noise LDO performance through its dedicated NMOS LI-LO controller architecture, which separates analog ground (AGND) and power ground (PGND_SW1/PGND_SW2), incorporates a precision 0.5 V internal reference with ±1.5% accuracy, and supports external feedback capacitor (C11) placement within 1 cm of LDOFB/LDO_OUT to suppress high-frequency instability. PSRR is −30 dB at 10 kHz, optimized for analog loads like ADC references and PLL VCO supplies.

LM26484SQ/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 24-WFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Digital Cores

Current - Supply:: -

Voltage - Supply:: 3V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-WQFN (4x5)

LM26484SQ/NOPB FAQ

1.How can I place an order for LM26484SQ/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for LM26484SQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LM26484SQ/NOPB reliable?

The price and inventory of LM26484SQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM26484SQ/NOPB is usually 5 days.

3.What payment methods are accepted for LM26484SQ/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM26484SQ/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LM26484SQ/NOPB?

LM26484SQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LM26484SQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LM26484SQ/NOPB?

For technical support, including LM26484SQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM26484SQ/NOPB requirements.

6.How does Aetrix verify that LM26484SQ/NOPB is sourced from the original manufacturer or authorized distributors?

All LM26484SQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM26484SQ/NOPB meets industry standards.

7.What is the process for return or replacement of LM26484SQ/NOPB?

All LM26484SQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM26484SQ/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LM26484SQ/NOPB part is unused and in its original packaging.

Return procedure for LM26484SQ/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…