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Texas Instruments LM5070MTC-50
- Part No.:
- LM5070MTC-50
- Manufacturer:
- Texas Instruments
- Category:
- Power Over Ethernet (PoE) Controllers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM5070MTC-50.pdf
- Description:
- IC POE CNTRL 1 CHANNEL 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,205
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Product details
Overview
LM5070MTC-50 from Texas Instruments is an IEEE 802.3af-compliant Powered Device (PD) interface and current-mode PWM controller with integrated 80V/400mA MOSFET, 50% maximum duty cycle limit (no slope compensation), programmable inrush current limit (75–390 mA), and UVLO with 2.00 V threshold. It enables PoE-powered endpoints such as VoIP phones and wireless access points requiring controlled startup and isolated/non-isolated dc-dc conversion.
For engineers reviewing the LM5070MTC-50 datasheet, LM5070MTC-50 pinout, LM5070MTC-50 application, or LM5070MTC-50 equivalent, key selection considerations include its -50 suffix duty-cycle limitation, TSSOP-16 package compatibility, PoE signature/classification compliance, and integration of PD interface sequencing with SMPS control - all critical for IEEE 802.3af Class 0–4 endpoint designs.
Technical Context
The LM5070MTC-50 implements a two-stage power sequencing architecture: first, the PD interface performs detection (1.8–10.0 V), classification (12.5–20.5 V), and inrush-limited charging via its internal 80V MOSFET; second, the current-mode PWM controller activates only after RTN falls below 1.5 V relative to VEE, ensuring proper power-good handoff. Its oscillator operates at twice the output frequency (e.g., 400 kHz internal for 200 kHz OUT) due to the on-chip divide-by-two circuit unique to the -50 variant.
This device supports both isolated (flyback/forward) and non-isolated topologies via FB/COMP error amplifier configuration, includes cycle-by-cycle current limiting triggered at 0.5 V on CS, and uses ARTN as dedicated analog ground for precision current sensing and soft-start timing - distinguishing it from general-purpose PWM controllers by its tightly coupled PoE-specific state machine and bias regulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| IEEE Compliance | Fully compliant with IEEE 802.3af detection, classification, and inrush timing requirements - enables plug-and-play interoperability with standard PSEs. |
| Max Duty Cycle | 50% with no slope compensation - constrains topology selection to duty-cycle-safe configurations (e.g., flyback with <50% max duty) without external ramp injection. |
| Inrush Current Limit | Programmable 75–390 mA via RCLP resistor - ensures ≤75 ms input capacitor charge time per IEEE 802.3af while accommodating legacy low-power PSEs. |
| UVLO Threshold | 2.00 V ±50 mV at UVLO pin - sets minimum operational input voltage (e.g., ~23 V min with divider); hysteresis enabled via 10 µA switched current source. |
| Oscillator Frequency | 175–225 kHz (OUT) with RT = 30.3 kΩ - actual internal oscillator runs at 350–450 kHz due to mandatory divide-by-two for -50 variant. |
| Internal MOSFET | 80 V VDSS, 1 Ω RDS(on), 400 mA continuous - handles full PoE interface switching without external FET, reducing BOM count and layout complexity. |
| Thermal Shutdown | 165 °C with 25 °C hysteresis - protects against sustained overload or poor heatsinking in enclosed PoE endpoint enclosures. |
Pinout & Package
TSSOP-16 (Package Code PW) with exposed thermal pad bonded to VEE; 5 mm × 4.4 mm footprint, 1.2 mm height, 0.65 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VIN | High-side input | Accepts diode-OR'd PoE input up to 75 V; supplies internal HV regulator and MOSFET drain. |
| 2 RSIG | Signature detection node | Connects 25 kΩ resistor to VIN to enable 23.75–26.25 kΩ impedance detection during PSE handshake. |
| 3 RCLASS | Classification current sink | Sinks programmable current (0–44 mA) to set IEEE 802.3af Class 0–4; open for Class 0 default. |
| 4 UVLO | UVLO sense input | Monitors resistor divider to trigger startup at 2.00 V; hysteresis added via internal 10 µA current source. |
| 5 UVLORTN | UVLO divider return | Reference node for UVLO divider - must not connect to VEE to avoid violating 10 µA detection offset spec. |
| 6 RCLP | Inrush current programming | Resistor here sets initial charge current (75–390 mA); open defaults to 390 mA. |
| 7 VEE | System low potential | Diode-OR'd return path for PoE lines; connects to internal MOSFET source and thermal pad. |
| 8 RTN | SMPS return / MOSFET source | Drain-to-source return for internal FET; used by detection circuitry to signal SMPS enable when <1.5 V vs VEE. |
| 9 OUT | PWM gate driver output | 800 mA peak sink capability drives external N-channel MOSFET gate; 50% max duty enforced internally. |
| 10 VCC | Internal bias regulator output | 7.8 V regulated supply (7.5–8.1 V) powers control circuitry; UVLO thresholds at 5.9–6.6 V falling/rising. |
| 11 FB | Error amplifier inverting input | Connects to voltage divider from SMPS output; 1.25 V internal reference enables precise output regulation. |
| 12 COMP | Error amp output / PWM input | Open-drain output with 5 kΩ internal pull-up; interfaces directly to optocoupler in isolated designs. |
| 13 CS | Current sense comparator input | Triggers cycle-by-cycle shutdown if ≥0.5 V; 55 ns leading-edge blanking suppresses switching noise. |
| 14 RT/SYNC | Oscillator timing & sync input | RT resistor sets frequency; accepts AC-coupled sync pulses >3.7 V peak for system-level clock alignment. |
| 15 SS | Soft-start ramp input | 10 µA internal current charges external capacitor to control PWM ramp-up and limit inrush stress. |
| 16 ARTN | Analog ground reference | Dedicated return for CS, RT, SS, FB, COMP - isolates noise-sensitive analog paths from power return. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PoE PD interface | Combines signature detection, classification, UVLO, and inrush control in one IC - eliminates discrete interface IC + controller combo. |
| 50% max duty cycle enforcement | Hardware-limited output prevents instability in current-mode converters operating near 50% duty - no external slope compensation needed. |
| Programmable inrush current | RCLP pin allows precise tuning of startup current (75–390 mA) to meet IEEE 802.3af timing while avoiding PSE overcurrent trips. |
| Dual-ground architecture | Separate RTN (power return) and ARTN (analog return) minimizes noise coupling between high-current switching and precision feedback paths. |
| Thermal shutdown with hysteresis | 165 °C trip point + 25 °C hysteresis prevents thermal oscillation during overload - critical for sealed PoE endpoint enclosures. |
Applications
| VoIP Phones | Wireless Access Points |
|---|---|
|
Use Scenario: Desktop IP phone powered exclusively via Cat5e Ethernet cable in enterprise LAN. IC Role / Device Role / Timing Role: LM5070MTC-50 acts as primary PD interface and flyback controller, managing IEEE 802.3af handshake, inrush limiting, and 3.3 V/5 V rail generation. Use Value: Enables single-cable deployment with guaranteed 75 ms input cap charge and Class 2 (3.84 W) classification support - eliminating local AC adapter. |
Use Scenario: Dual-band Wi-Fi 5 access point mounted on ceiling, drawing power from midspan PSE. IC Role / Device Role / Timing Role: LM5070MTC-50 provides PoE interface sequencing and controls isolated flyback converter delivering 12 V for RF front-end and 3.3 V for SoC. Use Value: Integrates detection, classification, and SMPS control with 50% duty cycle safety - simplifies layout and meets EN 62368-1 creepage/clearance for Class II isolation. |
| Network Cameras | Thin Clients |
|
Use Scenario: PTZ security camera with IR illumination, deployed outdoors using weatherproof PoE injector. IC Role / Device Role / Timing Role: LM5070MTC-50 manages cold-start under low-temperature conditions (<−20 °C), regulates auxiliary 5 V rail, and monitors current limit during motor surge. Use Value: Programmable RCLP resistor ensures reliable startup down to −40 °C ambient while maintaining IEEE 802.3af compliance - avoids brownout resets during pan/tilt motion. |
Use Scenario: Zero-client terminal in digital signage kiosk, powered via endpoint PSE in retail environment. IC Role / Device Role / Timing Role: LM5070MTC-50 serves as non-isolated buck controller (via FB/COMP) and PoE interface, generating 1.1 V core and 1.8 V I/O rails from 48 V PoE. Use Value: Error amplifier with 1.25 V reference and 75 dB DC gain enables tight output regulation (±1%) across load transients - critical for memory and display timing stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Powered Device interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5070MTC-80 | 80% max duty cycle with slope compensation; identical pinout and PoE interface functionality. | Supports higher-duty topologies (e.g., forward converter) and >50% duty operation where required. | Select LM5070MTC-80 only if design requires >50% duty cycle; LM5070MTC-50 is preferred for flyback with inherent duty limitation. |
| LT4275AIMSE#TRPBF | IEEE 802.3at/af-compliant PD interface only (no PWM controller); requires external dc-dc controller. | Used in designs needing PoE+ (30 W) support or multi-rail SMPS with independent controller optimization. | Choose LT4275AIMSE#TRPBF when upgrading to PoE+ or requiring flexible controller selection; LM5070MTC-50 integrates both functions. |
Compared with LM5070MTC-80 and LT4275AIMSE#TRPBF, the LM5070MTC-50 uniquely combines PoE interface compliance with a hardware-enforced 50% duty cycle PWM controller in TSSOP-16 - reducing component count for cost-sensitive Class 0–3 endpoints where duty cycle headroom is not required.
Availability
LM5070MTC-50 is available at Aetrix Electronics and suitable for VoIP phones, wireless access points, network cameras, and thin clients requiring stable component supply, long-term lifecycle assurance, and IEEE 802.3af interoperability.
Supply support for LM5070MTC-50 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in power management ICs.
The LM5070 product line delivers integrated Power over Ethernet Powered Device solutions targeting cost-effective, space-constrained endpoints that require full IEEE 802.3af compliance without external interface components.
FAQ
What is the key functional difference between LM5070MTC-50 and LM5070MTC-80?
The LM5070MTC-50 enforces a hardware-limited 50% maximum duty cycle with no slope compensation, while the LM5070MTC-80 supports up to 80% duty cycle with built-in slope compensation. Both share identical pinout, PoE interface features, and TSSOP-16 packaging. The -50 variant is optimized for flyback converters where duty cycle is inherently limited, reducing design complexity and external component count compared to the -80 version.
Does LM5070MTC-50 support IEEE 802.3at (PoE+)?
No, LM5070MTC-50 is designed exclusively for IEEE 802.3af (PoE) compliance, supporting up to 15.4 W at the PSE and 12.95 W at the PD. It lacks the dual-signature detection, extended classification, and higher-power inrush handling required for 802.3at. For PoE+ applications, TI recommends alternatives like the TPS23754 or LT4275 series, which are explicitly qualified for 802.3at.
How is the inrush current limit programmed on LM5070MTC-50?
The inrush current limit on LM5070MTC-50 is set by connecting a resistor between the RCLP pin (Pin 6) and VEE. Using Equation (1) from the datasheet, RCLP = (0.5 V × 10⁶) / ILIM, where ILIM is the desired current in mA. For example, a 160 kΩ resistor programs 3.125 mA × 100 = 312.5 mA. Leaving RCLP open defaults to 390 mA, matching the IEEE 802.3af maximum.
Can LM5070MTC-50 be used in non-isolated buck converter designs?
Yes, LM5070MTC-50 supports non-isolated applications via its internal error amplifier and reference. Connect the FB pin to a resistor divider from the output rail, configure COMP as open-drain with optional optocoupler bypass, and route power stage feedback directly. The 1.25 V reference, 75 dB DC gain, and 4 MHz GBW enable stable regulation of 3.3 V or 5 V outputs - confirmed in TI's SNVA229 application note for buck-mode operation.
What is the purpose of the ARTN pin on LM5070MTC-50?
The ARTN pin on LM5070MTC-50 serves as the dedicated analog ground return for noise-sensitive circuits including CS, RT, SS, FB, and COMP. It is electrically separate from RTN (power return) to prevent switching noise from corrupting current sensing, soft-start timing, and feedback signals. TI specifies routing ARTN directly to the VEE plane only at a single point near the IC - preserving signal integrity in high-EMI PoE environments.
LM5070MTC-50 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Type:
- Controller (PD), DC/DC
- Number of Channels:
- 1
- Power - Max:
- -
- Internal Switch(s):
- Both
- Auxiliary Sense:
- No
- Standards:
- 802.3af (PoE)
- Voltage - Supply:
- 1.8V ~ 75V
- Current - Supply:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
LM5070MTC-50 FAQ
1.How can I place an order for LM5070MTC-50 through Aetrix?
Please submit a Request for Quotation (RFQ) for LM5070MTC-50 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM5070MTC-50 reliable?
The price and inventory of LM5070MTC-50 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM5070MTC-50 is usually 5 days.
3.What payment methods are accepted for LM5070MTC-50?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM5070MTC-50 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM5070MTC-50?
LM5070MTC-50 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM5070MTC-50 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM5070MTC-50?
For technical support, including LM5070MTC-50 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM5070MTC-50 requirements.
6.How does Aetrix verify that LM5070MTC-50 is sourced from the original manufacturer or authorized distributors?
All LM5070MTC-50 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM5070MTC-50 meets industry standards.
7.What is the process for return or replacement of LM5070MTC-50?
All LM5070MTC-50 units undergo pre-shipment inspection (PSI). If there is an issue with LM5070MTC-50, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM5070MTC-50 part is unused and in its original packaging.
Return procedure for LM5070MTC-50:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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