Monolithic Power Systems Inc. MP8007GV-Z

Overview

MP8007GV-Z from Monolithic Power Systems is a fully integrated IEEE 802.3af-compliant Powered Device (PD) interface with primary-side regulated flyback or buck DC-DC converter, delivering up to 13W output power. It integrates a 100V/0.48Ω hot-swap MOSFET, 120mA inrush current limit, and 840mA operational current limit, and supports auxiliary wall-adapter ORing for dual-input PoE systems. Used in security cameras and VoIP phones requiring compact, isolated or non-isolated PoE power conversion.

For engineers reviewing the MP8007GV-Z datasheet, MP8007GV-Z pinout, MP8007GV-Z application, or MP8007GV-Z equivalent, key selection criteria include PD classification compliance (Class 0–3), primary-side regulation capability without optocoupler, 180V internal switching MOSFET rating, thermal shutdown at 150°C, and QFN-28 package compatibility with high-density PCB layouts.

Technical Context

The MP8007GV-Z implements a dual-mode DC-DC controller supporting both flyback (MODE = GND) and buck (MODE floating) topologies using fixed peak-current, variable-frequency DCM control. Its PD interface executes full 802.3af detection (1.9–11V threshold), classification (programmable via RCLASS), and mark-event sequencing - including 2-event classification for Type-2 PSE identification.

Internal protection includes overcurrent foldback triggered at VRTN ≥10V for >1ms, open-circuit detection on FB1 (−90 to −20mV), 125% VREF1-based OVP, and independent thermal shutdown (150°C/20°C hysteresis) for both PD and DC-DC sections. The AUX pin enables seamless wall-adapter priority detection by comparing VDD–VAUX against −2.3V reference.

Key Specifications

Pinout & Package

MP8007GV-Z is housed in a thermally enhanced QFN-28 (4mm × 5mm) package with exposed thermal pad connected to RTN/GND for efficient heat dissipation. Pin 1 (AUX) enables wall-adapter detection; pins 12/13 (SW) drive the internal 180V MOSFET; pins 20/21 (RTN) serve as hot-swap drain return; pins 23/24 (VSS) form the negative PoE input rail.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD interface applications.

Compared with LT4275IMS#PBF and TPS23753APWR, MP8007GV-Z uniquely combines PoE PD interface, dual-mode (flyback/buck) DC-DC, and AUX-based ORing in one QFN-28 package - reducing component count by 7 parts versus discrete controller+FET solutions while enabling flexible single- or dual-input system architectures.

Availability

MP8007GV-Z is available at Aetrix Electronics and suitable for security camera deployments, VoIP phone manufacturing, and WLAN access point production requiring stable component supply and long-term lifecycle support.

Supply support for MP8007GV-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of expertise in DC-DC conversion, PoE, and motor drive solutions.

The MP8007 belongs to MPS's PoE PD interface product line, engineered specifically for compact, cost-optimized 802.3af-compliant endpoints where integration of detection, classification, and regulated DC-DC conversion reduces design complexity and time-to-market.

FAQ

What is the maximum supported PoE input voltage for MP8007GV-Z?

The MP8007GV-Z supports a PoE input voltage range of 0V to 57V on the VDD–VSS rails, with absolute maximum ratings up to 100V on VDD and RTN pins. Its 100V hot-swap MOSFET and 180V internal switching FET ensure robust operation across the full IEEE 802.3af voltage envelope, including transient surges common in long Ethernet cable runs.

Can MP8007GV-Z operate with both flyback and buck topologies in the same design?

No - the topology is selected at power-up via the MODE pin: connecting MODE to GND configures flyback mode, while leaving it floating selects buck mode. The device does not support dynamic reconfiguration; changing topology requires hardware modification and reset. Both modes share the same FB1/FB2 feedback architecture but differ in transformer usage and output isolation.

How does the AUX pin enable wall-adapter ORing functionality?

The AUX pin compares VDD–VAUX against an internal −2.3V reference. When VDD–VAUX exceeds this threshold, the IC disables the hot-swap MOSFET, deactivates CLASS/T2P signaling, and asserts PG - effectively switching power source from PoE to the wall adapter. An external resistor divider sets the exact adapter detection voltage, and Schottky diodes prevent backfeed between sources.

What is the purpose of the T2P pin, and when does it assert?

The T2P pin is an open-drain output that pulls low to VSS to indicate either Type-2 PSE detection or successful wall-adapter activation. It asserts after the 80–100ms TDELAY following UVLO startup, provided VRTN has risen above 1.2V. In adaptor mode, T2P remains active low regardless of PSE presence, providing firmware with unambiguous power-source status.

Does MP8007GV-Z support IEEE 802.3at (PoE+) operation?

The MP8007GV-Z implements 802.3at-compatible detection and classification circuitry (including 2-event classification), but its DC-DC converter is rated only for 13W output - limiting practical use to 802.3af (Type-1) applications. While it can negotiate with Type-2 PSEs, sustained >13W loading will trigger thermal shutdown or current foldback, making it unsuitable for full 802.3at deployments.

What is the recommended minimum output capacitor for stable regulation in buck mode?

In buck mode, MPS recommends a minimum 47μH inductor and ≥22μF ceramic output capacitor (X5R/X7R, 16V rating) placed close to SW, GND, and VOUT pins. This ensures stable DCM operation at 200kHz switching frequency and maintains ≤100mV output ripple under 2.5A load steps, as verified in the MP8007EV evaluation board layout guidelines.