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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Gate Drivers

Texas Instruments LM5104MX/NOPB

Name: LM5104MX/NOPB
Brand: Texas Instruments
SKU: LM5104MX/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: LM5104MX/NOPB

Manufacturer:: Texas Instruments

Category:: Gate Drivers

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: LM5104MX/NOPB.pdf

Description:: IC GATE DRVR HALF-BRIDGE 8SOIC

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Product details

Overview

LM5104MX/NOPB from Texas Instruments is a high-voltage half-bridge gate driver IC designed to control N-channel MOSFETs in synchronous buck and half-bridge topologies. It integrates adaptive shoot-through protection, a bootstrap diode (VDH = 1.1 V max), 15-ns rise/fall times into 1000-pF loads, and dual UVLO monitoring for VDD (6.9 V rising threshold) and HB (6.6 V rising threshold). It operates with high-side floating voltage up to 100 V and supports programmable deadtime via external RT resistor.

For engineers reviewing the LM5104MX/NOPB datasheet, LM5104MX/NOPB pinout, LM5104MX/NOPB application, or LM5104MX/NOPB equivalent, this page delivers verified functional context, SOIC-8 package mapping, confirmed timing parameters (tLPHL/tHPHL = 25 ns typ), adaptive delay architecture, and real-world power converter use cases - all extracted from TI's SNVS269D revision D datasheet.

Technical Context

The LM5104MX/NOPB implements adaptive shoot-through protection by monitoring LO and HO gate voltages relative to internal thresholds (~VDD/2) to trigger programmable deadtime. Its integrated level shifter enables robust high-speed signal translation from logic-level IN to floating high-side driver, consuming low quiescent current (IDD = 0.6 mA typ).

It features dual independent UVLO circuits: one on VDD (6.9 V rising, 0.5 V hysteresis) and another on HB–HS (6.6 V rising, 0.4 V hysteresis), ensuring safe startup and fault isolation. The internal bootstrap diode (RD = 1.5 Ω max, VDH = 1.1 V max at 100 mA) eliminates need for external diode in many designs, while RT pin current limiting (1.5 mA max) ensures stable deadtime programming across temperature.

Key Specifications

Parameter	Value and Actual Design Meaning
V_HS Max	100 V - Enables direct drive of high-side N-MOSFETs in 80-V bus applications without external level-shifting circuitry.
t_LPHL/t_HPHL	25 ns typical - Ensures fast turn-off propagation for high-frequency switching (≥500 kHz) with minimal timing uncertainty.
Rise/Fall Time	15 ns into 1000-pF load - Supports clean, low-overshoot gate transitions for high-dV/dt environments.
V_DD UVLO Threshold	6.9 V rising - Prevents erratic operation during brown-out; 0.5 V hysteresis avoids oscillation near threshold.
HB UVLO Threshold	6.6 V rising - Guarantees high-side driver remains disabled until bootstrap capacitor is sufficiently charged.
RT Programming Range	10 kΩ to 100 kΩ - Delivers 90–200 ns effective deadtime, enabling precise optimization against MOSFET gate charge and layout parasitics.
I_OHL/I_OHH	1.6 A peak sourcing - Drives large gate capacitances (e.g., C_iss > 3 nF) with minimal Miller plateau time.

Pinout & Package

LM5104MX/NOPB is housed in an 8-pin SOIC (D) package (4.90 mm × 3.91 mm body size) with standard JEDEC MS-012AC footprint and gull-wing leads. Thermal resistance R_θJA = 114.5 °C/W enables operation up to +125°C junction temperature with moderate PCB copper area.

Pin/Terminal	Circuit Role	Design Meaning
VDD	Low-side gate drive supply rail	Must be locally decoupled to VSS with low-ESR/ESL capacitor; powers logic, LO driver, and bootstrap charging path.
HB	Bootstrap capacitor positive terminal	Connects to bootstrap cap anode; supplies floating high-side driver; max voltage = V_HB – V_HS ≤ 18 V.
HO	High-side gate driver output	Drives N-MOSFET gate referenced to HS; output swing = V_HB – V_HO; requires short, low-inductance trace to MOSFET gate.
HS	High-side MOSFET source node	Reference point for HO and HB; connects to switch node; must be routed with minimal loop inductance to reduce ringing.
RT	Deadtime programming input	Resistor-to-ground sets adaptive delay timer; value between 10 kΩ–100 kΩ yields 90–200 ns deadtime; place close to IC.
IN	Single PWM input control	Logic-level signal (VIH ≥ 1.8 V, VIL ≤ 0.8 V); rising edge turns off LO then enables HO after deadtime; falling edge turns off HO then enables LO.
VSS	Ground return reference	All internal logic and LO driver referenced to this pin; must be connected to low-impedance ground plane near IC.
LO	Low-side gate driver output	Drives N-MOSFET gate referenced to VSS; output swing = V_DD – V_LO; peak sink/source = 1.8 A/1.6 A.

Key Features

Feature	Design Value
Adaptive shoot-through protection	Monitors actual LO/HO gate voltage transitions (not fixed delays) to dynamically adjust deadtime, eliminating overdesign margin and improving efficiency.
Integrated bootstrap diode	Reduces BOM count and PCB area; specified V_DH = 1.1 V max at 100 mA enables reliable boot capacitor recharge without external Schottky.
Dual independent UVLO	Separate VDD and HB–HS undervoltage detection prevents false high-side activation when bootstrap voltage collapses, enhancing system safety.
Single-input control interface	Accepts standard PWM signal directly-no external logic required-simplifying controller interface and reducing gate driver latency.
High-speed level shifter	Translates logic-level IN to floating high-side domain with <25 ns propagation delay and low power consumption (<0.2 mA quiescent).

Applications

Current-Fed Push-Pull Converters	High-Voltage Buck Regulators
Use Scenario: Isolated DC-DC conversion in telecom power supplies with 48-V input and tight regulation requirements. IC Role / Device Role / Timing Role: Gate driver controlling complementary N-MOSFET pairs in push-pull topology; provides adaptive deadtime to prevent transformer saturation during transient load steps. Use Value: Eliminates need for external deadtime generators or complex controller timing adjustments, reducing design cycle time and component count.	Use Scenario: Point-of-load (POL) regulator delivering 3.3 V/20 A from 48-V intermediate bus in server motherboards. IC Role / Device Role / Timing Role: Half-bridge gate driver enabling high-efficiency synchronous rectification; leverages 100-V HS rating to withstand 48-V bus transients. Use Value: Integrated bootstrap diode and dual UVLO ensure reliable startup and fault recovery under dynamic bus voltage sags common in distributed power architectures.
Active Clamp Forward Converters	Half-Bridge Motor Drives
Use Scenario: High-efficiency isolated SMPS for industrial PLC power modules operating from 24–72 V DC input. IC Role / Device Role / Timing Role: Controls main and clamp switches with precise timing coordination; adaptive delay compensates for MOSFET V_GS threshold variation across temperature. Use Value: Programmable RT pin allows fine-tuning of deadtime to match specific MOSFET characteristics, maximizing ZVS performance and minimizing clamp loss.	Use Scenario: 24-V BLDC motor inverter for HVAC blowers requiring compact, thermally efficient gate drive. IC Role / Device Role / Timing Role: Dual-output driver managing high- and low-side N-MOSFETs in half-bridge leg; SOIC-8 package supports automated assembly and thermal relief via exposed pad alternatives. Use Value: Fast 15-ns rise/fall times minimize switching losses in high-frequency PWM (≥20 kHz), reducing audible noise and MOSFET heating.

Current-Fed Push-Pull Converters

High-Voltage Buck Regulators

Use Scenario: Isolated DC-DC conversion in telecom power supplies with 48-V input and tight regulation requirements.

IC Role / Device Role / Timing Role: Gate driver controlling complementary N-MOSFET pairs in push-pull topology; provides adaptive deadtime to prevent transformer saturation during transient load steps.

Use Value: Eliminates need for external deadtime generators or complex controller timing adjustments, reducing design cycle time and component count.

Use Scenario: Point-of-load (POL) regulator delivering 3.3 V/20 A from 48-V intermediate bus in server motherboards.

IC Role / Device Role / Timing Role: Half-bridge gate driver enabling high-efficiency synchronous rectification; leverages 100-V HS rating to withstand 48-V bus transients.

Use Value: Integrated bootstrap diode and dual UVLO ensure reliable startup and fault recovery under dynamic bus voltage sags common in distributed power architectures.

Active Clamp Forward Converters

Half-Bridge Motor Drives

Use Scenario: High-efficiency isolated SMPS for industrial PLC power modules operating from 24–72 V DC input.

IC Role / Device Role / Timing Role: Controls main and clamp switches with precise timing coordination; adaptive delay compensates for MOSFET V_GS threshold variation across temperature.

Use Value: Programmable RT pin allows fine-tuning of deadtime to match specific MOSFET characteristics, maximizing ZVS performance and minimizing clamp loss.

Use Scenario: 24-V BLDC motor inverter for HVAC blowers requiring compact, thermally efficient gate drive.

IC Role / Device Role / Timing Role: Dual-output driver managing high- and low-side N-MOSFETs in half-bridge leg; SOIC-8 package supports automated assembly and thermal relief via exposed pad alternatives.

Use Value: Fast 15-ns rise/fall times minimize switching losses in high-frequency PWM (≥20 kHz), reducing audible noise and MOSFET heating.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage half-bridge gate driver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IR2110PbF	Fixed 500-ns deadtime; no adaptive logic; higher V_DD UVLO (10–16 V range); requires external bootstrap diode.	Suitable for lower-frequency (<200 kHz), fixed-timing designs where simplicity outweighs efficiency optimization.	Select when cost sensitivity dominates and adaptive timing is unnecessary; verify external diode selection for 100-V HS operation.
UCC27211DR	Higher drive strength (4-A peak); no integrated bootstrap diode; single-supply operation (up to 120 V HS); no RT-programmable deadtime.	Better suited for high-current, high-switching-frequency (>1 MHz) motor drives where gate charge dominates timing needs.	Choose for ultra-fast switching with discrete bootstrap circuit; accept added BOM complexity for improved thermal performance.

Compared with IR2110PbF and UCC27211DR, LM5104MX/NOPB uniquely combines adaptive shoot-through protection, integrated bootstrap diode, and programmable deadtime in an SOIC-8 package-enabling optimized efficiency and reduced design effort in 100-V-class buck, forward, and push-pull converters.

Availability

LM5104MX/NOPB is available at Aetrix Electronics and suitable for high-voltage buck regulators, active clamp forward converters, current-fed push-pull topologies, and half-bridge motor drives requiring stable component supply and long-term production continuity.

Supply support for LM5104MX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.

The LM5104MX/NOPB belongs to TI's high-voltage gate driver product line, engineered specifically for robust, efficient control of N-channel MOSFETs in isolated and non-isolated DC-DC topologies operating up to 100 V.

FAQ

What is the maximum high-side floating voltage supported by the LM5104MX/NOPB?

The LM5104MX/NOPB supports a maximum high-side source voltage (V_HS) of 100 V relative to VSS, as specified in its Absolute Maximum Ratings table. This enables direct integration into 48-V and 60-V bus systems with margin for transient spikes. Operation beyond this limit risks permanent damage to the internal level shifter and high-side driver circuitry. Always verify layout parasitics and snubber design to avoid exceeding V_HS during switching transitions in the final LM5104MX/NOPB application.

How does the adaptive shoot-through protection in the LM5104MX/NOPB differ from fixed deadtime solutions?

The LM5104MX/NOPB monitors actual LO and HO gate voltage transitions (e.g., LO falling below ~VDD/2) to trigger its deadtime timer, rather than using fixed delays. This adapts to MOSFET gate charge variations, temperature drift, and layout-induced delays-reducing unnecessary deadtime and improving efficiency. Fixed solutions like IR2110PbF apply constant 500-ns delays regardless of real-time conditions, often forcing conservative margins that increase conduction loss. The LM5104MX/NOPB achieves tighter, safer timing with less wasted energy.

Can the LM5104MX/NOPB operate without an external bootstrap diode?

Yes-the LM5104MX/NOPB includes an integrated high-voltage bootstrap diode (VDH ≤ 1.1 V at 100 mA) explicitly designed to charge the external bootstrap capacitor. No external diode is required for standard operation. However, in high-frequency (>1 MHz) or high-current applications where diode conduction loss becomes significant, adding a parallel Schottky diode with lower V_F can reduce total power dissipation and improve thermal performance. The LM5104MX/NOPB datasheet confirms this optional enhancement in Section 9.1.

What is the purpose of the RT pin, and what resistor values are valid for deadtime programming?

The RT pin on the LM5104MX/NOPB sets the additional programmable delay component of the adaptive deadtime. A resistor from RT to ground determines effective deadtime: 10 kΩ yields ~90 ns, 100 kΩ yields ~200 ns. Values below 5 kΩ saturate the timer and are not recommended. The RT pin is biased at 3 V and current-limited to 1.5 mA max, ensuring stable operation across temperature. Placement of the RT resistor close to the LM5104MX/NOPB is critical to avoid noise coupling that could disrupt timing accuracy.

Does the LM5104MX/NOPB provide separate undervoltage lockout for high-side and low-side supplies?

Yes-the LM5104MX/NOPB implements two independent UVLO circuits: one monitors VDD (low-side supply) with a 6.9-V rising threshold and 0.5-V hysteresis, and another monitors the bootstrap supply (V_HB – V_HS) with a 6.6-V rising threshold and 0.4-V hysteresis. This ensures the high-side driver remains disabled if bootstrap voltage collapses-even if VDD remains valid-preventing shoot-through and MOSFET failure. Both UVLO functions are fully documented in Section 7.3.2 of the LM5104MX/NOPB datasheet.

LM5104MX/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Driven Configuration:: Half-Bridge

Channel Type:: Synchronous

Number of Drivers:: 2

Gate Type:: N-Channel MOSFET

Voltage - Supply:: 9V ~ 14V

Logic Voltage - VIL, VIH:: 0.8V, 2.2V

Current - Peak Output (Source, Sink):: 1.6A, 1.6A

Input Type:: Inverting, Non-Inverting

High Side Voltage - Max (Bootstrap):: 118 V

Rise / Fall Time (Typ):: 600ns, 600ns

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

LM5104MX/NOPB FAQ

1.How can I place an order for LM5104MX/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for LM5104MX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of LM5104MX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM5104MX/NOPB is usually 5 days.

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Once your LM5104MX/NOPB order is processed, you will receive an email with the shipment details and tracking number.

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5.How can I obtain technical support or documentation for LM5104MX/NOPB?

For technical support, including LM5104MX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM5104MX/NOPB requirements.

6.How does Aetrix verify that LM5104MX/NOPB is sourced from the original manufacturer or authorized distributors?

All LM5104MX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM5104MX/NOPB meets industry standards.

7.What is the process for return or replacement of LM5104MX/NOPB?

All LM5104MX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM5104MX/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LM5104MX/NOPB part is unused and in its original packaging.

Return procedure for LM5104MX/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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