Texas Instruments LM5106SD/NOPB

Overview

LM5106SD/NOPB from Texas Instruments is a 100-V half-bridge gate driver IC designed to concurrently drive high-side and low-side N-channel MOSFETs in synchronous buck or half-bridge topologies. It delivers 1.8-A peak sink and 1.2-A peak source current, supports bootstrap supply up to 118 V DC, features programmable dead-time via external resistor (RDT), and integrates independent UVLO for VDD and HB rails. It is used in solid-state motor drives and two-switch forward converters.

For engineers reviewing the LM5106SD/NOPB datasheet, LM5106SD/NOPB pinout, LM5106SD/NOPB application, or LM5106SD/NOPB equivalent, key selection criteria include its 100-V HS rail capability, TTL-compatible dual-input control (IN/EN), 32-ns typical turnoff propagation delay, 15-ns rise/10-ns fall time into 1000 pF, and WSON-10 thermal performance (θ_JA = 37.9°C/W).

Technical Context

The LM5106SD/NOPB employs robust level-shift technology to enable high-speed, low-power floating high-side drive with clean output transitions. Its internal dead-time generator uses a single RDT resistor (5 kΩ–100 kΩ) to set matched turn-on delays for both HO and LO outputs, ranging from 100 ns to 600 ns.

Independent undervoltage lockout circuits monitor VDD (6.9 V rising threshold, 0.5 V hysteresis) and HB–HS (6.6 V rising threshold, 0.4 V hysteresis), disabling respective drivers when thresholds are violated. The EN pin provides TTL-compatible enable/disable control with hysteresis, while IN controls phase logic with complementary HO/LO output states.

Key Specifications

Pinout & Package

The LM5106SD/NOPB is housed in a 4 mm × 4 mm thermally enhanced 10-pin WSON package (DPR) with exposed pad connected to system ground for improved thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with LM5106SD/NOPB, LM5109BMT/NOPB trades programmability for higher drive strength and simpler control, while UCC27211DRCR offers greater voltage headroom and integration at the cost of HB UVLO safety margin-making LM5106SD/NOPB optimal for cost-sensitive, thermally constrained half-bridge designs requiring tunable dead-time and dual-rail protection.

Availability

LM5106SD/NOPB is available at Aetrix Electronics and suitable for solid-state motor drives, half-bridge power converters, and two-switch forward power supplies requiring stable component supply, long-term industrial lifecycle support, and consistent WSON-10 thermal performance.

Supply support for LM5106SD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability industrial and automotive-grade ICs.

The LM5106SD/NOPB belongs to TI's high-voltage gate driver product line, engineered specifically for robust, efficient control of N-channel MOSFETs in isolated and non-isolated DC-DC and motor drive topologies operating up to 100 V.

FAQ

What is the maximum allowable voltage on the HS pin of the LM5106SD/NOPB?

The LM5106SD/NOPB specifies a maximum HS-to-VSS voltage of 100 V. During normal operation, the HS node is clamped by the body diode of the low-side MOSFET and typically remains ≥ –1 V. However, transient negative excursions are permitted down to VDD − 15 V (e.g., –5 V if VDD = 10 V), provided HO remains > HS − 0.3 V to avoid parasitic conduction. This limit ensures safe operation in hard-switching and fast-decay motor drive scenarios.

How does the RDT pin program dead-time in the LM5106SD/NOPB?

The RDT pin on the LM5106SD/NOPB is internally biased at 3.0 V and accepts an external resistor (5–100 kΩ) to VSS. This resistor sets matched turn-on delays for both HO and LO outputs, yielding a dead-time range of 100–600 ns. For example, a 100-kΩ resistor produces ~570 ns typical dead-time, while 10 kΩ yields ~115 ns. The LM5106SD/NOPB's internal timing circuit ensures tight matching (<50 ns mismatch) between DT1 and DT2, critical for preventing shoot-through in bridge configurations.

Does the LM5106SD/NOPB support independent control of high-side and low-side outputs?

No-the LM5106SD/NOPB uses a single IN input to define complementary HO/LO states (IN high = HO high / LO low; IN low = HO low / LO high), with dead-time automatically inserted between transitions. It does not support independent PWM inputs for each output. The EN pin provides global enable/disable but does not alter the phase relationship. For true independent control, designers must select alternatives like the UCC272xx family or dual-driver solutions.

What is the purpose of the exposed pad on the LM5106SD/NOPB WSON package?

The exposed pad on the LM5106SD/NOPB WSON-10 package has no electrical function but serves a critical thermal role: it must be soldered to the PCB's internal or external ground plane to reduce junction-to-board thermal resistance (θ_JB = 14.9°C/W). This improves power dissipation capability and stabilizes junction temperature during sustained 1.8-A sink operation-especially vital in motor drive and high-duty-cycle converter applications where thermal margin is constrained.

Can the LM5106SD/NOPB drive MOSFETs with gate charges exceeding 50 nC?

Yes-the LM5106SD/NOPB can drive MOSFETs with gate charges exceeding 50 nC, provided layout minimizes trace inductance and gate resistors are selected to manage dV/dt and ringing. Its 1.8-A peak sink and 1.2-A peak source currents enable sub-100-ns turnoff/turnon into high-C_iss devices. For a 60-nC MOSFET at 200 kHz, average gate drive power remains within LM5106SD/NOPB's thermal limits when using the WSON package with proper PCB copper area, as confirmed by TI's measured power dissipation curves in SNVS424D.