Texas Instruments LMG1205YFXT
- Part No.:
- LMG1205YFXT
- Manufacturer:
- Texas Instruments
- Category:
- Gate Drivers
- Package:
- 12-WFBGA, DSBGA
- Datasheet:
-
LMG1205YFXT.pdf
- Description:
- IC GATE DRVR HALF-BRIDGE 12DSBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMG1205YFXT from Texas Instruments is a 100-V, high-frequency half-bridge GaN gate driver IC with integrated bootstrap diode, delivering 1.2-A peak source and 5-A sink current per channel, 35-ns typical propagation delay, and split-gate outputs for independent turnon/turnoff control - used to drive enhancement-mode GaN FETs in MHz-class synchronous buck and half-bridge converters.
For engineers reviewing the LMG1205YFXT datasheet, LMG1205YFXT pinout, LMG1205YFXT application, or LMG1205YFXT equivalent, key selection considerations include bootstrap voltage clamping at 5 V, TTL-compatible inputs tolerant to 14 V, 1.5-ns typical LO/HO propagation delay matching, 0.6-Ω pulldown / 2.1-Ω pullup output resistance, and DSBGA-12 package with minimized inductance for high-dv/dt immunity.
Technical Context
The LMG1205YFXT implements a floating high-side level-shift architecture with internal 5-V HB-to-HS clamp, enabling safe operation with 100-V HS rail swing while preventing GaN FET overvoltage. Its dual independent TTL inputs (HI/LI) interface directly with PWM controllers up to 14 V, eliminating external level-shifting circuitry.
Split-gate outputs (HOH/HOL, LOH/LOL) provide discrete control of turnon strength (via HOH/LOH) and turnoff strength (via HOL/LOL), supported by 0.6-Ω pulldown and 2.1-Ω pullup resistances optimized for fast GaN switching and ringing suppression. Undervoltage lockout (UVLO) operates separately on VDD (3.8 V threshold) and HB–HS (3.2 V threshold), each with 200-mV hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VDD) | 4.5 V to 5.5 V - powers low-side driver and logic; UVLO activates below 3.8 V to prevent partial FET turnon. |
| High-Side Bias Range (HB–HS) | 4 V to 5.5 V - bootstrap rail clamped at 5 V typical to protect GaN gate oxide; withstands 100-V HS rail. |
| Peak Output Current | 1.2-A source / 5-A sink - enables rapid GaN gate charging/discharging for sub-10-ns edge rates and MHz operation. |
| Propagation Delay | 35 ns typical (LO/ HO) - ensures precise timing alignment critical for dead-time control in hard-switched topologies. |
| Delay Matching | 1.5 ns typical (LO vs HO) - minimizes shoot-through risk by tightly synchronizing high- and low-side switching edges. |
| Input Voltage Tolerance | 0 V to 14 V - allows direct interfacing with 3.3-V, 5-V, or 12-V PWM controllers without external buffers. |
| Output Resistance | 0.6 Ω (pulldown), 2.1 Ω (pullup) - balances fast turnoff (dv/dt immunity) and controlled turnon (ringing suppression). |
Pinout & Package
LMG1205YFXT is housed in a 2.00 mm × 2.00 mm, 12-pin DSBGA (YFX) package optimized for minimal parasitic inductance and thermal performance (RθJA = 76.8°C/W). The ultra-compact footprint supports high-density GaN power stage layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1: LOL | Low-side sink-current output | Drives GaN FET gate low; connects via short, low-inductance path; gate resistor adjusts turnoff speed. |
| A2: VSS | Ground return | Common reference for all signals; must be low-impedance connection to PCB ground plane. |
| A3/C4: VDD | 5-V gate drive supply | Powers low-side logic and driver; requires local 0.1-µF ceramic decoupling capacitor placed adjacent to pins. |
| A4: LI | Low-side input (TTL) | Active-high control signal; unused pins must be tied to VSS (not left floating). |
| B1: LOH | Low-side source-current output | Drives GaN FET gate high; paired with LOL for split-gate control; gate resistor adjusts turnon speed. |
| B4: HI | High-side input (TTL) | Active-high control signal referenced to VSS; tolerant to 14-V input regardless of VDD level. |
| C1/D4: HS | High-side source node | Connects to bootstrap capacitor negative terminal and high-side GaN FET source; handles –5 V to +100 V swing. |
| D1: HOL | High-side sink-current output | Turns off high-side GaN FET; referenced to HS; gate resistor fine-tunes turnoff edge and dv/dt immunity. |
| D2: HOH | High-side source-current output | Turns on high-side GaN FET; referenced to HS; works with HOL for independent strength adjustment. |
| D3: HB | Bootstrap rail supply | Connects to positive terminal of bootstrap capacitor; internally clamped at 5 V to protect GaN gate. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 100-V bootstrap diode | Eliminates external diode, reduces BOM count, and enables compact layout - forward voltage 0.45 V (100 µA), 0.9 V (100 mA). |
| Split-gate outputs (HOH/HOL, LOH/LOL) | Allows independent optimization of turnon slew rate (via HOH/LOH) and turnoff robustness (via HOL/LOL) for GaN-specific EMI and reliability trade-offs. |
| Internal 5-V HB–HS clamp | Prevents gate-source overvoltage during negative HS transients or bootstrap overshoot - clamping delay <270 ns, regulation ±0.25 V over temperature. |
| TTL-compatible inputs with 14-V tolerance | Directly interfaces with industry-standard PWM controllers (e.g., UCC2897A, LM5113) without level shifters or voltage dividers. |
| Strong 5-A sink capability | Ensures reliable gate discharge under high dv/dt conditions, suppressing unintended turnon in fast-switching GaN half-bridges. |
Applications
| Current-Fed Push-Pull Converters | Half-Bridge DC-DC Converters |
|---|---|
Use Scenario: High-efficiency isolated DC-DC conversion in telecom and server PSUs using push-pull topology with GaN switches. IC Role / Device Role / Timing Role: LMG1205YFXT drives complementary GaN FET pairs with matched propagation delay to maintain symmetrical duty cycle and minimize transformer core imbalance. Use Value: 1.5-ns LO/HO delay matching prevents flux walking; integrated bootstrap diode simplifies auxiliary winding elimination. |
Use Scenario: 48-V input to 12-V output point-of-load converter operating at 1 MHz in datacenter power delivery. IC Role / Device Role / Timing Role: LMG1205YFXT serves as dual-channel gate driver controlling high- and low-side GaN FETs in hard-switched half-bridge configuration. Use Value: 5-A sink current ensures clean turnoff under 100-V/ns dv/dt; 0.6-Ω pulldown resistance suppresses Miller-induced false turnon. |
| Synchronous Buck Converters | Forward Converters with Active Clamp |
Use Scenario: High-density 12-V intermediate bus converter for FPGA/ASIC power rails requiring >95% efficiency at 1 MHz. IC Role / Device Role / Timing Role: LMG1205YFXT provides split-gate control to independently tune high-side turnon (HOH) and turnoff (HOL) for optimal trade-off between conduction loss and switching loss. Use Value: 2.1-Ω pullup resistance damps switch-node ringing; 35-ns propagation enables tight dead-time control down to 8 ns. |
Use Scenario: Isolated 400-V to 48-V telecom rectifier using active-clamp forward topology with GaN primary switches. IC Role / Device Role / Timing Role: LMG1205YFXT drives main and clamp GaN FETs with independent TTL inputs (HI/LI), enabling precise phase relationship and zero-voltage switching initiation. Use Value: 100-V HS rail rating supports wide input range; internal UVLO on HB–HS prevents clamp FET misfiring during startup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar GaN half-bridge gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMG1210YFQ | Higher 1.8-A source / 6-A sink current; identical 12-pin DSBGA package and pinout; adds programmable dead-time control. | Targeted at higher-power GaN designs (>1 kW) requiring enhanced drive strength and timing flexibility. | Select LMG1210YFQ when driving larger GaN FETs (Qg > 25 nC) or needing digital dead-time tuning via I²C interface. |
| UCC27611DR | Single-channel, 5-A sink / 2.5-A source driver; SOIC-8 package; no integrated bootstrap diode or high-side level shift. | Requires external high-side driver or isolated supply; suited for low-cost, non-GaN or asymmetrical topologies. | Choose UCC27611DR only in conjunction with a separate high-side solution (e.g., ISO5852S) and where board space permits discrete bootstrap circuitry. |
Compared with LMG1210YFQ, the LMG1205YFXT offers lower drive strength but simpler control and cost; versus UCC27611DR, it delivers full half-bridge integration with GaN-optimized features - making LMG1205YFXT the preferred choice for compact, high-frequency GaN half-bridge designs requiring minimal external components.
Availability
LMG1205YFXT is available at Aetrix Electronics and suitable for high-frequency power conversion, GaN-based DC-DC modules, and telecom/server power supplies requiring stable component supply, consistent parametric performance, and long-term production continuity.
Supply support for LMG1205YFXT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-performance gate drivers and GaN ecosystem development.
The LMG1205YFXT belongs to TI's GaN-optimized gate driver product line, engineered specifically for MHz-class switching with enhancement-mode GaN FETs in high-density, high-efficiency power conversion systems.
FAQ
What is the maximum allowable HS-to-VSS voltage for LMG1205YFXT?
The LMG1205YFXT supports an absolute maximum HS-to-VSS voltage of 100 V under pulsed conditions (1000 pulses, <1% duty, 100 ms max), and 90 V under continuous operation per recommended conditions. This rating enables use in 48-V and 60-V bus applications with margin for transient overvoltage.
Does LMG1205YFXT require an external bootstrap diode?
No, the LMG1205YFXT integrates a 100-V-rated bootstrap diode with 0.45-V forward voltage at 100 µA. External diodes are unnecessary and not recommended unless bypassing the internal clamp - in which case the internal diode is disabled per datasheet Section 7.3.3.
How does the internal 5-V HB–HS clamp protect the GaN FET in LMG1205YFXT?
The LMG1205YFXT clamps HB–HS to 5 V ±0.25 V to prevent exceeding the typical 6-V maximum gate-source voltage of enhancement-mode GaN FETs. It activates within ~270 ns of threshold exceedance, using an internal switch in series with the bootstrap diode to halt further charging.
Can LMG1205YFXT drive both high-side and low-side GaN FETs simultaneously in a synchronous buck?
Yes, the LMG1205YFXT is explicitly designed for synchronous buck, boost, and half-bridge configurations. Its independent HI/LI inputs, split-gate outputs (HOH/HOL, LOH/LOL), and matched 35-ns propagation delays enable precise, coordinated control of both GaN FETs with minimal shoot-through risk.
What is the purpose of the split-gate outputs in LMG1205YFXT?
The split-gate outputs (HOH/HOL and LOH/LOL) allow independent adjustment of turnon and turnoff strength via external gate resistors. HOH/LOH control rise time and ringing; HOL/LOL control fall time and dv/dt immunity - essential for optimizing EMI and reliability in GaN-based converters.
LMG1205YFXT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 12-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Half-Bridge
- Channel Type:
- Independent
- Number of Drivers:
- 2
- Gate Type:
- N-Channel MOSFET
- Voltage - Supply:
- 4.5V ~ 5.5V
- Logic Voltage - VIL, VIH:
- 1.76V, 1.89V
- Current - Peak Output (Source, Sink):
- 1.2A, 5A
- Input Type:
- TTL
- High Side Voltage - Max (Bootstrap):
- 100 V
- Rise / Fall Time (Typ):
- 7ns, 3.5ns
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DSBGA
LMG1205YFXT FAQ
1.How can I place an order for LMG1205YFXT through Aetrix?
Please submit a Request for Quotation (RFQ) for LMG1205YFXT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMG1205YFXT reliable?
The price and inventory of LMG1205YFXT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMG1205YFXT is usually 5 days.
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LMG1205YFXT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMG1205YFXT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMG1205YFXT?
For technical support, including LMG1205YFXT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMG1205YFXT requirements.
6.How does Aetrix verify that LMG1205YFXT is sourced from the original manufacturer or authorized distributors?
All LMG1205YFXT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMG1205YFXT meets industry standards.
7.What is the process for return or replacement of LMG1205YFXT?
All LMG1205YFXT units undergo pre-shipment inspection (PSI). If there is an issue with LMG1205YFXT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMG1205YFXT part is unused and in its original packaging.
Return procedure for LMG1205YFXT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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